MX25L12845E
Continuously Program Mode( CP mode) bit. The Continuously Program Mode bit indicates the status of CP
mode, "0" indicates not in CP mode; "1" indicates in CP mode.
Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. This bit will also
be set when the user attempts to program a protected main memory region or a locked OTP region. This bit can in-
dicate whether one or more of program operations fail, and can be reset by command CLSR (30h)
Erase Fail Flag bit. While a erase failure happened, the Erase Fail Flag bit would be set. This bit will also be set
when the user attempts to erase a protected main memory region or a locked OTP region. This bit can indicate
whether one or more of erase operations fail, and can be reset by command CLSR (30h)
Write Protection Select bit. The Write Protection Select bit indicates that WPSEL has been executed successfully.
Once this bit has been set (WPSEL=1), all the blocks or sectors will be write-protected after the power-on every
time. Once WPSEL has been set, it cannot be changed again, which means it's only for individual WP mode.
Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once
WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits.
Security Register Definition
bit7
bit6
bit5
bit4
bit3
x
bit2
x
bit1
bit0
Continuously
Program
mode
(CP mode)
LDSO
(indicate if
lock-down
Secrured
OTP
indicator bit
WPSEL
E_FAIL
P_FAIL
0 = not
lockdown
1 = lock-
down
(cannot
program/
erase
0=normal
Erase
succeed
1=indicate
Erase failed
(default=0)
0=normal
Program
succeed
1=indicate
Program
failed
0=normal
WP mode
1=individual
WP mode
(default=0)
0 =
nonfactory
lock
1 = factory
lock
0=normal
Program
mode
1=CP mode
(default=0)
reserved
reserved
(default=0)
OTP)
non-volatile
bit
non-volatile non-volatile
bit bit
volatile bit
volatile bit
volatile bit
volatile bit
volatile bit
(27) Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN
instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values
of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Se-
cured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
P/N: PM1428
REV. 0.06, MAR. 05, 2009
29
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