Hig h -Effic ie n c y, P WM, S t e p -Do w n
DC-DC Co n t ro lle rs in 1 6 -P in QS OP
Power from the main and secondary outputs is lumped
together to obtain an equivalent current referred to the
main output voltage (see Inductor Value section for def-
initions of parameters). Set the value of the current-
In high-current applications, MOSFET package power
dissipation often becomes a dominant design factor.
2
I R losses are distributed between Q1 and Q2 accord-
ing to duty factor (see the equations below). Switching
los s e s a ffe c t the up p e r MOSFET only, s inc e the
Schottky rectifier clamps the switching node before the
synchronous rectifier turns on. Gate-charge losses are
dissipated by the driver and don’t heat the MOSFET.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications. The worst-case dissi-
pation for the high-side MOSFET occurs at the minimum
battery voltage, and the worst-case for the low-side
MOSFET occurs at the maximum battery voltage.
2
sense resistor at 80mV / I
.
TOTAL
P
= the sum of the output power from
all outputs
TOTAL
I
= P
/ V
= the equivalent output
TOTAL
TOTAL
OUT
current referred to V
OUT
V
(V
- V
)
OUT IN(MAX)
OUT
L(primary) = —————————————
x f x I x LIR
V
IN(MAX)
TOTAL
V
SEC
+ V
FWD
Turns Ratio N = ——————————————
+ V + V
V
OUT(MIN)
RECT
SENSE
PD (upper FET) = I
x R
x DUTY
LOAD
DS(ON)
where:
V
is the minimum required rectified
SEC
V
x C
RSS
IN
secondary-output voltage
+ V x I
x f x
(
––––––––––– +20ns
)
IN
LOAD
I
GATE
2–MAX165
V
is the forward drop across the
FWD
2
secondary rectifier
PD (lower FET) = I
x R
x (1 - DUTY)
LOAD
DS(ON)
V
is the minimum value of the main
DUTY = (V
+ V ) / (V - V + V
)
OUT(MIN)
OUT
Q2
IN
Q1
Q2
output voltage (from the Electrical
Characteristics)
where the on-state voltage drop V = I
x R
DS(ON)
Q_
LOAD
C
= MOSFET reverse transfer capacitance
RSS
V
RECT
is the on-state voltage drop across the
I
= DH driver peak output current capability
(1A typically)
GATE
synchronous-rectifier MOSFET
V
SENSE
is the voltage drop across the sense
20ns = DH driver inherent rise/fall time
resistor
Under output short circuit, the synchronous-rectifier
MOSFET suffers extra stress and may need to be over-
sized if a continuous DC short circuit must be tolerated.
During short circuit, Q2’s duty factor can increase to
greater than 0.9 according to:
In positive-output (MAX1652) applications, the trans-
former secondary return is often referred to the main
output voltage rather than to ground in order to reduce
the needed turns ratio. In this case, the main output
voltage must first be subtracted from the secondary
voltage to obtain V
.
Q2 DUTY (short circuit) = 1 - [V / (V
- V
V )]
SEC
Q2
IN(MAX)
Q1 + Q2
where the on-state voltage drop V = (120mV / R
)
Q
SENSE
______S e le c t in g Ot h e r Co m p o n e n t s
MOS FET S w it c h e s
The two high-current N-channel MOSFETs must be
logic-level types with guaranteed on-resistance specifi-
x R
DS(ON).
Re c t ifie r Dio d e D1
Rectifier D1 is a clamp that catches the negative induc-
tor swing during the 60ns dead time between turning
off the high-side MOSFET and turning on the low-side.
D1 must be a Schottky type in order to prevent the
lossy parasitic MOSFET body diode from conducting. It
is acceptable to omit D1 and let the body diode clamp
the negative inductor swing, but efficiency will drop one
or two percent as a result. Use an MBR0530 (500mA
rated) type for loads up to 1.5A, a 1N5819 type for
loads up to 3A, or a 1N5822 type for loads up to 10A.
D1’s rated reverse breakdown voltage must be at least
equal to the maximum input voltage, preferably with a
20% derating factor.
cations at V = 4.5V. Lower gate threshold specs are
GS
better (i.e., 2V max rather than 3V max). Drain-source
breakdown voltage ratings must at least equal the max-
imum input voltage, preferably with a 20% derating
factor. The best MOSFETs will have the lowest on-resis-
tance per nanocoulomb of gate charge. Multiplying
R
x Q provides a meaningful figure by which to
DS(ON)
G
compare various MOSFETs. Newer MOSFET process
technologies with dense cell structures generally give
the best performance. The internal gate drivers can tol-
erate more than 100nC total gate charge, but 70nC is a
more practical upper limit to maintain best switching
times.
22 ______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
