Hig h -Effic ie n c y, P WM, S t e p -Do w n
DC-DC Co n t ro lle rs in 1 6 -P in QS OP
the DH gate-driver peak output current (1A typ), and
20ns is the rise/fall time of the DH driver.
__________Ap p lic a t io n s In fo rm a t io n
He a vy-Lo a d Effic ie n c y Co n s id e ra t io n s
The major efficiency loss mechanisms under loads (in
the usual order of importance) are:
2
P(cap) = input capacitor ESR loss = (I
) x R
RMS
ESR
where I
is the input ripple current as calculated in the
RMS
Input Capacitor Value section of the Design Procedure.
2
2
• P(I R), I R losses
• P(gate), gate-charge losses
• P(diode), diode-conduction losses
• P(tran), transition losses
• P(cap), capacitor ESR losses
Lig h t -Lo a d Effic ie n c y Co n s id e ra t io n s
Under light loads, the PWM operates in discontinuous
mode, where the inductor current discharges to zero at
some point during the switching cycle. This causes the
AC component of the inductor current to be high com-
pared to the load current, which increases core losses
• P(IC), losses due to the operating supply current
of the IC
2
and I R losses in the output filter capacitors. Obtain best
light-load efficiency by using MOSFETs with moderate
gate-charge levels and by using ferrite, MPP, or other
low-loss core material. Avoid powdered iron cores; even
Kool-mu (aluminum alloy) is not as good as ferrite.
Ind uc tor-c ore los s e s a re fa irly low a t he a vy loa d s
because the inductor’s AC current component is small.
Therefore, they aren’t accounted for in this analysis.
Ferrite cores are preferred, especially at 300kHz, but
powdered cores such as Kool-mu can work well.
__P C Bo a rd La yo u t Co n s id e ra t io n s
2–MAX165
Good PC board layout is required to achieve specified
noise, efficiency, and stability performance. The PC
b oa rd la yout a rtis t mus t b e p rovid e d with e xp lic it
instructions, preferably a pencil sketch of the place-
ment of power switching components and high-current
routing. See the evaluation kit PC board layouts in the
MAX1653, MAX796, and MAX797 EV kit manuals for
examples. A ground plane is essential for optimum per-
formance. In most applications, the circuit will be locat-
ed on a multilayer board, and full use of the four or
more copper layers is recommended. Use the top layer
for high-current connections, the bottom layer for quiet
connections (REF, SS, GND), and the inner layers for
an uninterrupted ground plane. Use the following step-
by-step guide.
Efficiency = P
= P
/ P x 100%
IN
OUT
OUT
2
/ (P
+ P
) x 100%
OUT
TOTAL
P
= P(I R) + P(gate) + P(diode) + P(tran) +
TOTAL
P(cap) + P(IC)
2
2
P(I R) = (I
) x (R
+ R
+ R
)
LOAD
DC
DS(ON)
SENSE
where R
is the DC resistance of the coil, R
is
DC
DS(ON)
the MOSFET on-resistance, and R
sense resistor value. The R
c a l MOSFETs for the hig h- a nd low-s id e s witc he s
because they time-share the inductor current. If the
MOSFETs aren’t identical, their losses can be estimat-
ed by averaging the losses according to duty factor.
is the current-
SENSE
term assumes identi-
DS(ON)
P(gate) = gate-driver loss = qG x f x VL
where VL is the MAX1652 internal logic supply voltage
(5V), and qG is the sum of the gate-charge values for
low- and high-side switches. For matched MOSFETs,
q G is twic e the d a ta s he e t va lue of a n ind ivid ua l
1) Place the high-power components (C1, C2, Q1, Q2,
D1, L1, and R1) first, with their grounds adjacent.
Priority 1: Minimize current-sense resistor trace
lengths (see Figure 9).
MOSFET. If V
is set to less than 4.5V, replace VL in
OUT
this equation with V
improved by connecting VL to an efficient 5V source,
such as the system +5V supply.
. In this case, efficiency can be
BATT
Priority 2: Minimize ground trace lengths in the
high-current paths (discussed below).
Priority 3: Minimize other trace lengths in the high-
current paths. Use >5mm wide traces.
C1 to Q1: 10mm max length. D1 anode to
Q2: 5mm ma x le ng th LX nod e (Q1
source, Q2 drain, D1 cathode, inductor):
15mm max length
P(diode) = diode conduction losses
= I
x V
x t x f
LOAD
FWD D
where t is the diode conduction time (120ns typ) and
D
V
FWD
is the forward voltage of the Schottky.
PD(tran) = transition loss =
Id e a lly, s urfa c e -mount p owe r c omp one nts a re
butted up to one another with their ground terminals
almost touching. These high-current grounds (C1-,
C2-, source of Q2, anode of D1, and PGND) are
then connected to each other with a wide filled zone
VBATT x CRSS
V
x I
x f x
(
——————— + 20ns
)
BATT LOAD
I
GATE
where C
is the reverse transfer capacitance of the
high-side MOSFET (a data sheet parameter), I
RSS
is
GATE
24 ______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
