Hig h -Effic ie n c y, P WM, S t e p -Do w n
DC-DC Co n t ro lle rs in 1 6 -P in QS OP
2–MAX165
of top-layer copper, so that they don’t go through
vias. The resulting top-layer “sub-ground-plane” is
connected to the normal inner-layer ground plane at
the output ground terminals. This ensures that the
analog GND of the IC is sensing at the output termi-
na ls of the s up p ly, without inte rfe re nc e from IR
drops and ground noise. Other high-current paths
should also be minimized, but focusing ruthlessly
on short ground and current-sense connections
eliminates about 90% of all PC board layout diffi-
culties. See the evaluation kit PC board layouts for
examples.
FAT, HIGH-CURRENT TRACES
MAIN CURRENT PATH
SENSE RESISTOR
2) Place the IC and signal components. Keep the main
switching node (LX node) away from sensitive ana-
log components (current-sense traces and REF and
SS capacitors). Placing the IC and analog compo-
nents on the opposite side of the board from the
power-switching node is desirable. Important: the
IC must be no farther than 10mm from the current-
sense resistor. Keep the gate-drive traces (DH, DL,
and BST) shorter than 20mm and route them away
from CSH, CSL, REF, and SS.
MAX1652
MAX1653
MAX1654
MAX1655
Figure 9. Kelvin Connections for the Current-Sense Resistor
3) Employ a single-point star ground where the input
ground trace, power ground (subground plane),
and normal ground plane all meet at the output
ground terminal of the supply.
P in Co n fig u ra t io n s
TOP VIEW
SS
SS
1
2
3
4
5
6
7
8
DH
LX
1
2
3
4
5
6
7
8
DH
LX
16
15
14
13
16
15
14
13
(SECFB) SKIP
REF
SKIP
REF
BST
DL
BST
DL
MAX1652
MAX1653
MAX1654
MAX1655
MAX1653
MAX1655
GND
GND
12 PGND
11 VL
12 PGND
11 VL
SYNC
SHDN
FB
SYNC
SHDN
FB
10 V+
10
9
V+
CSH
CSL
CSH
CSL
9
QSOP
Narrow SO
( ) ARE FOR MAX1652/MAX1654.
______________________________________________________________________________________ 25
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
