DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
THIR: TRANSMIT HDLC INFORMATION REGISTER (Address = B6 Hex)
(MSB)
(LSB)
—
—
—
—
—
TEMPTY
TFULL
TUDR
SYMBOL POSITION
NAME AND DESCRIPTION
—
—
—
—
—
THIR.7
THIR.6
THIR.5
THIR.4
THIR.3
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Transmit FIFO Empty. A real-time bit that is set high when the FIFO is
empty.
TEMPTY
TFULL
TUDR
THIR.2
THIR.1
THIR.0
Transmit FIFO Full. A real-time bit that is set high when the FIFO is
full.
Transmit FIFO Underrun. Set when the transmit FIFO empties out
without the TEOM control bit being set. An abort is automatically sent.
Note: The TUDR bit is latched and is cleared when read.
THFR: TRANSMIT HDLC FIFO REGISTER (Address = B7 Hex)
(MSB)
(LSB)
HDLC7
HDLC6
HDLC5
HDLC4
HDLC3
HDLC2
HDLC1
HDLC0
SYMBOL POSITION
NAME AND DESCRIPTION
HDLC7
HDLC6
HDLC5
HDLC4
HDLC3
HDLC2
HDLC1
HDLC0
THFR.7
THFR.6
THFR.5
THFR.4
THFR.3
THFR.2
THFR.1
THFR.0
HDLC Data Bit 7. MSB of a HDLC packet data byte.
HDLC Data Bit 6.
HDLC Data Bit 5.
HDLC Data Bit 4.
HDLC Data Bit 3.
HDLC Data Bit 2.
HDLC Data Bit 1.
HDLC Data Bit 0. LSB of a HDLC packet data byte.
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
