DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
RHIR: RECEIVE HDLC INFORMATION REGISTER (Address = B3 Hex)
(MSB)
(LSB)
RABT
RCRCE
ROVR
RVM
REMPTY
POK
CBYTE
OBYTE
SYMBOL POSITION
NAME AND DESCRIPTION
Abort Sequence Detected. Set whenever the HDLC controller sees 7 or
RABT
RCRCE
ROVR
RHIR.7
RHIR.6
RHIR.5
more ones in a row.
CRC Error. Set when the CRC checksum is in error.
Overrun. Set when the HDLC controller has attempted to write a byte
into an already full receive FIFO.
Valid Message. Set when the HDLC controller has detected and checked
a complete HDLC packet.
RVM
RHIR.4
RHIR.3
REMPTY
Empty. A real-time bit that is set high when the receive FIFO is empty.
Packet OK. Set when the byte available for reading in the receive FIFO at
RHFR is the last byte of a valid message (and hence no abort was seen, no
overrun occurred, and the CRC was correct).
POK
RHIR.2
Closing Byte. Set when the byte available for reading in the receive FIFO
at RHFR is the last byte of a message (whether the message was valid or
not).
CBYTE
OBYTE
RHIR.1
RHIR.0
Opening Byte. Set when the byte available for reading in the receive
FIFO at RHFR is the first byte of a message.
Note: The RABT, RCRCE, ROVR, and RVM bits are latched and are cleared when read.
RHFR: RECEIVE HDLC FIFO REGISTER (Address = B4 Hex)
(MSB)
(LSB)
HDLC7
HDLC6
HDLC5
HDLC4
HDLC3
HDLC2
HDLC1
HDLC0
SYMBOL POSITION
NAME AND DESCRIPTION
HDLC Data Bit 7. MSB of a HDLC packet data byte.
HDLC Data Bit 6.
HDLC7
HDLC6
HDLC5
HDLC4
HDLC3
HDLC2
HDLC1
HDLC0
RHFR.7
RHFR.6
RHFR.5
RHFR.4
RHFR.3
RHFR.2
RHFR.1
RHFR.0
HDLC Data Bit 5.
HDLC Data Bit 4.
HDLC Data Bit 3.
HDLC Data Bit 2.
HDLC Data Bit 1.
HDLC Data Bit 0. LSB of a HDLC packet data byte.
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
