DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
14.4. HDLC Register Description
HCR: HDLC CONTROL REGISTER (Address = B0 Hex)
(MSB)
(LSB)
—
RHR
TFS
THR
TABT
TEOM
TZSD
TCRCD
SYMBOL POSITION
NAME AND DESCRIPTION
Not Assigned. Should be set to zero when written.
—
HCR.7
HCR.6
Receive HDLC Reset. A 0-to-1 transition will reset the HDLC controller.
Must be cleared and set again for a subsequent reset.
Transmit Flag/Idle Select.
RHR
TFS
HCR.5
HCR.4
0 = 7Eh
1 = FFh
Transmit HDLC Reset. A 0-to-1 transition will reset the HDLC
controller. Must be cleared and set again for a subsequent reset.
Transmit Abort. A 0-to-1 transition will cause the FIFO contents to be
dumped and one FEh abort to be sent followed by 7Eh or FFh flags/idle
until a new packet is initiated by writing new data into the FIFO. Must be
cleared and set again for a subsequent abort to be sent.
Transmit End of Message. Should be set to a one just before the last data
byte of a HDLC packet is written into the transmit FIFO at THFR. This bit
will be cleared by the HDLC controller when the last byte has been
transmitted.
THR
TABT
TEOM
HCR.3
HCR.2
Transmit Zero Stuffer Defeat. Overrides internal enable.
0 = enable the zero stuffer (normal operation)
TZSD
HCR.1
HCR.0
1 = disable the zero stuffer
Transmit CRC Defeat.
TCRCD
0 = enable CRC generation (normal operation)
1 = disable CRC generation
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