DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
HIMR: HDLC INTERRUPT MASK REGISTER (Address = B2 Hex)
(MSB)
(LSB)
FRCL
RPE
RPS
RHALF
RNE
THALF
TNF
TMEND
SYMBOL POSITION
NAME AND DESCRIPTION
Framer Receive Carrier Loss.
0 = interrupt masked
1 = interrupt enabled
Receive Packet End.
0 = interrupt masked
1 = interrupt enabled
Receive Packet Start.
0 = interrupt masked
1 = interrupt enabled
Receive FIFO Half Full.
0 = interrupt masked
1 = interrupt enabled
Receive FIFO Not Empty.
0 = interrupt masked
1 = interrupt enabled
Transmit FIFO Half Empty.
0 = interrupt masked
1 = interrupt enabled
Transmit FIFO Not Full.
0 = interrupt masked
1 = interrupt enabled
Transmit Message End.
0 = interrupt masked
1 = interrupt enabled
FRCL
HIMR.7
HIMR.6
HIMR.5
HIMR.4
HIMR.3
HIMR.2
HIMR.1
HIMR.0
RPE
RPS
RHALF
RNE
THALF
TNF
TMEND
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
