DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
14. HDLC CONTROLLER FOR THE Sa BITS OR DS0
The DS21354/DS21554 can extract/insert data from/into the Sa bit positions (Sa4 to Sa8) or from/to any
multiple of DS0 or sub-DS0 channels. The SCT contains a complete HDLC controller (see Section 14).
14.1. General Overview
The DS21354/DS21554 contain a complete HDLC controller with 64-byte buffers in both the transmit
and receive directions The HDLC controller performs all the necessary overhead for generating and
receiving an HDLC formatted message.
The HDLC controller automatically generates and detects flags, generates and checks the CRC check
sum, generates and detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns
to the HDLC data stream.
There are 11 registers that the host uses to operate and control the operation of the HDLC controller. A
brief description of the registers is shown in Table 14-1.
Table 14-1. HDLC Controller Register List
NAME
FUNCTION
HDLC Control Register (HCR)
HDLC Status Register (HSR)
HIMR Interrupt Mask Register (HIMR)
general control over the HDLC controller
key status information for both transmit and receive
directions allows/stops status bits to/from causing an
interrupt
Receive HDLC Information register (RHIR)
Receive HDLC FIFO Register (RHFR)
status information on receive HDLC controller
access to 64–byte HDLC FIFO in receive direction
Receive HDLC DS0 Control Register 1 (RDC1) controls the HDLC function when used on DS0
Receive HDLC DS0 Control Register 2 (RDC2) channels
controls the HDLC function when used on DS0
channels
Transmit HDLC Information register (THIR)
Transmit HDLC FIFO Register (THFR)
status information on transmit HDLC controller
access to 64–byte HDLC FIFO in transmit direction
Transmit HDLC DS0 Control Register 1 (TDC1) controls the HDLC function when used on DS0
Transmit HDLC DS0 Control Register 2 (TDC2) channels
controls the HDLC function when used on DS0
channels
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
