DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Figure 18-15. DS21354/DS21554 Transmit Data Flow
TSER
&
TDATA
HDLC
ENGINE
TNAF.0-4
0
0
1
1
Sa Data Source
DS0 Data
MUX
Source MUX
(TDC1/2)
(TDC1)
RSER
(note #1)
TAF
TNAF.5-7
1
TLINK
TC1toTC32
1
0
0
TAF/TNAF Bit
MUX
Per-Channel Code
Generation
(TCC1/2/3/4)
0
1
Timeslot 0
Pass-Through
(TCR1.6)
1
0
Si Bit Insertion
Control
(TCR1.3)
Receive Side
CRC4 Error
Detector
CRC4 Multiframe
Alignment Word
Generation (CCR.4)
0
1
E-Bit Generation
(TCR2.1)
0
1
SaBit Insertion
TSiAF
TSiNAF
TRA
Control (TCR2.3
thruTCR2.7)
TIDR
0
TIR Function Select
(CCR3.5)
1
TSa4toTSa8
AutoRemoteAlarm
Generation (CCR2.4)
0
1
SaBit Insertion
Control Register
(TSaCR)
AIS
Generation
TS1 to TS16
0
1
IdleCode/ Channel
Insertion Control via
TIR1/2/3/4
0
1
Transmit Signaling
All Ones
(TCR1.2)
TCBR1/2/3/4
CCR3.6
0
1
Signaling Bit
InsertionControl
Code Word
Generation
TCR1.5
KEY:
0
1
CRC4 Enable
= Register
(CCR.4)
AIS
Generation
= Device Pin
= Selector
0
1
Transmit Unframed All
Ones (TCR1.4) or
Auto AIS (CCR2.5)
NOTES:
1. TCLKshouldbe tiedtoRCLKand TSYNCshouldbe tiedtoRFSYNCfor
datato be properly sourcedfromRSER.
2. Auto Remote Alarm if enabled will only overwrite bit 3 of timeslot 0 in the
Not Align Frames if the alarm needs to be sent.
AMI or HDB3
Converter
CCR1.6
To Waveshaping
and Line DriversTPOS,
110 of 124
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