71M6543F/H and 71M6543G/GH Data Sheet
Sometimes it is desirable to prevent the SPI interface from writing to arbitrary RAM locations and thus
disturbing MPU and CE operation. This is especially true in AFE applications. For this reason, the SPI
SAFE mode was created. In SPI SAFE mode, SPI write operations are disabled except for a 16 byte
transfer region at address 0x400 to 0x40F. If the SPI host needs to write to other addresses, it must use
the SPI_CMD register to request the write operation from the MPU. SPI SAFE mode is enabled by the
SPI_SAFE bit (I/O RAM 0x270C[3]).
Single-Byte Transaction
If a transaction is a single byte, the byte is interpreted as SPI_CMD. Regardless of the byte value,
single-byte transactions always update the SPI_CMD register and cause an SPI interrupt to be generated.
Multi-Byte Transaction
As shown in Figure 23, multi-byte operations consist of a 16 bit address field, an 8 bit CMD, a status byte,
and a sequence of data bytes. A multi byte transaction is three or more bytes.
SERIAL READ
Status Byte
16 bit Address
DATA[ADDR]
8 bit CMD
DATA[ADDR+1]
(From Host) SPI_CSZ
(From Host) SPI_CK
(From Host) SPI_DI
(From 6543) SPI_DO
Extended Read . . .
0
15
A0
16
23
24
31
32
x
39
40
47
A15 A14
A1
C7
C6
C5
C0
HI Z
ST7 ST6 ST5
ST0 D7
D6
D1
D0
D7
D6
D1
D0
SERIAL WRITE
Status Byte
DATA[ADDR]
DATA[ADDR+1]
16 bit Address
8 bit CMD
(From Host) SPI_CSZ
(From Host) SPI_CK
(From Host) SPI_DI
(From 6543) SPI_DO
Extended Write . . .
40
0
15
16
23
24
31
32
39
47
A14
x
x
A15
A1
A0
C7
C6
C5
C0
D7
D6
D1
D0
D7
D6
D1
D0
HI Z
ST7 ST6 ST5
ST0
Figure 23: SPI Slave Port - Typical Multi-Byte Read and Write operations
Table 58: SPI Command Sequences
Command Sequence
Description
Read data starting at ADDR. ADDR is auto-incremented until SPI_CSZ
is raised. Upon completion, SPI_CMD (SFR 0xFD) is updated to 1xxx xxxx
and an SPI interrupt is generated. The exception is if the command
byte is 1000 0000. In this case, no MPU interrupt is generated and
SPI_CMD is not updated.
ADDR 1xxx xxxx STATUS
Byte0 ... ByteN
Write data starting at ADDR. ADDR is auto-incremented until SPI_CSZ is
raised. Upon completion, SPI_CMD is updated to 0xxx xxxx and an SPI
interrupt is generated. The exception is if the command byte is 0000
0000. In this case, no MPU interrupt is generated and SPI_CMD is not
updated.
0xxx xxxx ADDR Byte0 ...
ByteN
Table 59: SPI Registers
Name
Location
2701[7]
Rst Wk Dir Description
EX_SPI
SPI_CMD
0
–
0
–
R/W SPI interrupt enable bit.
SFR FD[7:0]
R
SPI command. The 8-bit command from the bus master.
SPI port enable bit. It enables the SPI interface on pins
SEGDIO36 – SEGDIO39.
SPI_E
270C[4]
SFR F8[7]
270C[3]
1
0
0
1
0
0
R/W
IE_SPI
R/W SPI interrupt flag. Set by hardware, cleared by writing a 0.
Limits SPI writes to SPI_CMD and a 16 byte region in
DRAM when set. No other write operations are permitted.
SPI_SAFE
R/W
70
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