71M6543F/H and 71M6543G/GH Data Sheet
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- With HiZ
SCLK (output)
D7
D6
D5
D4
D3
D2
SDATA (output)
SDATA output Z
BUSY (bit)
(LoZ)
(HiZ)
Figure 19: 3-wire Interface. Write Command, HiZ=1
EECTRL Byte Written
INT5
CNT Cycles (8 shown)
READ
SCLK (output)
D7
D6
D5
D4
D3
D2
D1
D0
SDATA (input)
SDATA output Z
BUSY (bit)
(HiZ)
Figure 20: 3-wire Interface. Read Command.
EECTRL Byte Written
EECTRL Byte Written
INT5 not issued
CNT Cycles (0 shown)
INT5 not issued
CNT Cycles (0 shown)
Write -- No HiZ
Write -- HiZ
SCLK (output)
SCLK (output)
D7
SDATA (output)
SDATA (output)
SDATA output Z
BUSY (bit)
(LoZ)
(HiZ)
SDATA output Z
BUSY (bit)
Figure 21: 3-Wire Interface. Write Command when CNT=0
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- With HiZ and WFR
SCLK (output)
D7
D6
D5
D4
D3
D2
BUSY
READY
SDATA (out/in)
(From 6520)
(From EEPROM)
(LoZ)
(HiZ)
SDATA output Z
BUSY (bit)
Figure 22: 3-wire Interface. Write Command when HiZ=1 and WFR=1.
2.5.12 SPI Slave Port
The slave SPI port communicates directly with the MPU data bus and is able to read and write Data RAM
and Configuration RAM (I/O RAM) locations. It is also able to send commands to the MPU. The interface
to the slave port consists of the SPI_CSZ, SPI_CKI, SPI_DI and SPI_DO pins. These pins are multiplexed
with the combined DIO/LCD segment driver pins SEGDIO36 to SEGDIO39 (pins 3, 2, 1 and 100).
Additionally, the SPI interface allows flash memory to be read and to be programmed. To facilitate flash
programming, cycling power or asserting RESET causes the SPI port pins to default to SPI mode. The
SPI port is disabled by clearing the SPI_E bit (I/O RAM 0x270C[4]).
Possible applications for the SPI interface are:
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