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71M6543H 参数 Datasheet PDF下载

71M6543H图片预览
型号: 71M6543H
PDF下载: 下载PDF文件 查看货源
内容描述: 可选增益1或8的一个电流电能表计量芯片的补偿 [Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation]
分类和应用:
文件页数/大小: 157 页 / 2164 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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71M6543F/H and 71M6543G/GH Data Sheet  
For example, if LCD_MAP[46] = 1, then pin 93 (TMUX2OUT/SEG46) is configured as SEG46, and if  
LCD_MAP[46]=0, then pin 93 is configured as TMUX2OUT.  
The SEG pins with alternate ICE interface function (see pins 56-58 in Figure 43) are forced to their  
alternate ICE interface function (i.e., E_RXTX, E_TCLK and E_RST) if the ICE_E pin (pin 59) is driven  
high, and in this case, the bits LCD_MAP[50:48] (I/O RAM 0x2405[2:0]) bits are “don’t care” bits. If the  
ICE_E pin is driven low, then LCD_MAP[50:48] bits must written with 1 in order to configure these pins as  
SEG pins. If the ICE_E pin is low and LCD_MAP[50:48] are written with 0, then these pins are tied to an  
internal pullup.  
2.5.11 EEPROM Interface  
The 71M6543 provides hardware support for either a two-pin or a three-wire (µ-wire) type of EEPROM  
interface. The interfaces use the EECTRL (SFR 0x9F) and EEDATA (SFR 0x9E) registers for communication.  
2.5.11.1 Two-pin EEPROM Interface  
The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is  
multiplexed onto the SEGDIO2 (SDCK) and SEGDIO3 (SDATA) pins and is selected by setting  
DIO_EEX[1:0] = 01 (I/O RAM 0x2456[7:6]). The MPU communicates with the interface through the SFR  
registers EEDATA and EECTRL. If the MPU wishes to write a byte of data to the EEPROM, it places the  
data in EEDATA and then writes the Transmit code to EECTRL. This initiates the transmit operation which  
is finished when the BUSY bit falls. INT5 is also asserted when BUSY falls. The MPU can then check the  
RX_ACK bit to see if the EEPROM acknowledged the transmission.  
A byte is read by writing the Receive command to EECTRL and waiting for the BUSY bit to fall. Upon  
completion, the received data is in EEDATA. The serial transmit and receive clock is 78 kHz during each  
transmission, and then holds in a high state until the next transmission. The EECTRL bits when the two-pin  
interface is selected are shown in Table 55.  
Table 55: EECTRL Bits for 2-pin Interface  
Status  
Bit  
Read/ Reset  
Write State  
Name  
Polarity Description  
ERROR  
BUSY  
7
6
5
R
R
R
0
0
1
Positive  
Positive  
Positive  
1 when an illegal command is received.  
1 when serial data bus is busy.  
RX_ACK  
1 indicates that the EEPROM sent an ACK bit.  
1 indicates when an ACK bit has been sent to the  
EEPROM.  
TX_ACK  
4
R
1
Positive  
Operation  
CMD[3:0]  
No-op command. Stops the I2C clock  
(SDCK). If not issued, SDCK keeps  
toggling.  
0000  
Receive a byte from the EEPROM and  
send ACK.  
0010  
CMD[3:0]  
3:0  
W
0000 Positive  
0011  
0101  
Transmit a byte to the EEPROM.  
Issue a STOP sequence.  
Receive the last byte from the  
EEPROM and do not send ACK.  
0110  
1001  
Issue a START sequence.  
No operation, set the ERROR bit.  
Others  
The EEPROM interface can also be operated by controlling the DIO2 and DIO3 pins directly. The  
direction of the DIO line can be changed from input to output and an output value can be written  
with a single write operation, thus avoiding collisions (see Table 14 Port Registers (SEGDIO0-15)).  
Therefore, no resistor is required in series SDATA to protect against collisions.  
66  
© 2008–2011 Teridian Semiconductor Corporation  
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