71M6543F/H and 71M6543G/GH Data Sheet
2.4
80515 MPU Core
The 71M6543 include an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock
cycle. Using a 4.9 MHz clock results in a processing throughput of 4.9 MIPS. The 80515 architecture
eliminates redundant bus states and implements parallel execution of fetch and execution phases. Normally, a
machine cycle is aligned with a memory fetch, therefore, most of the 1-byte instructions are performed in a
single machine cycle (MPU clock cycle). This leads to an 8x average performance improvement (in terms of
MIPS) over the Intel 8051 device running at the same clock frequency.
Table 8 shows the CKMPU frequency as a function of the MCK clock (19.6608 MHz) divided by the MPU
clock divider MPU_DIV[2:0] (I/O RAM 0x2200[2:0]). Actual processor clocking speed can be adjusted to the
total processing demand of the application (metering calculations, AMR management, memory
management, LCD driver management and I/O management) using MPU_DIV[2:0], as shown in Table 8.
Table 8: CKMPU Clock Frequencies
CKMPU Frequency
MPU_DIV [2:0]
000
001
010
011
100
101
110
111
4.9152 MHz
2.4576 MHz
1.2288 MHz
614.4 kHz
307.2 kHz
Typical measurement and metering functions based on the results provided by the internal 32-bit compute
engine (CE) are available for the MPU as part of the Teridian demonstration code, which is provided to
help reduce the product design cycle.
2.4.1 Memory Organization and Addressing
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces. Memory
organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas:
Program memory (Flash, shared by MPU and CE), external RAM (Data RAM, shared by the CE and MPU,
Configuration or I/O RAM), and internal data memory (Internal RAM). Table 9 shows the memory map.
Program Memory
The 80515 can address up to 64 KB of program memory space (0x0000 to 0xFFFF). Program memory is
read when the MPU fetches instructions or performs a MOVC operation.
After reset, the MPU starts program execution from program memory location 0x0000. The lower part of
the program memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte
intervals, starting from 0x0003.
MPU External Data Memory (XRAM)
Both internal and external memory is physically located on the 71M6543 device. The external memory
referred to in this documentation is only external to the 80515 MPU core.
5 KB of RAM starting at address 0x0000 is shared by the CE and MPU. The CE normally uses the first
1 KB, leaving 4 KB for the MPU. Different versions of the CE code use varying amounts. Consult the
documentation for the specific code version being used for the exact limit.
If the MPU overwrites the CE’s working RAM, the CE’s output may be corrupted. If the CE is dis-
abled, the first 0x40 bytes of RAM are still unusable while MUX_DIV[3:0] ≠ 0 (I/O RAM 0x2100[7:3]),
because the 71M6543 ADC writes to these locations. Writing MUX_DIV[3:0] = 0 disables the ADC
output, preventing the CE from writing the first 0x40 bytes of RAM.
In addition, MUXn_SEL[3:0] values must be written only after writing MUX_DIV[3:0].
30
© 2008–2011 Teridian Semiconductor Corporation
v1.2
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
