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71M6543H 参数 Datasheet PDF下载

71M6543H图片预览
型号: 71M6543H
PDF下载: 下载PDF文件 查看货源
内容描述: 可选增益1或8的一个电流电能表计量芯片的补偿 [Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation]
分类和应用:
文件页数/大小: 157 页 / 2164 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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71M6543F/H and 71M6543G/GH Data Sheet  
The WPULSE and VPULSE pulse generator outputs are available on pins SEGDIO0/WPULSE and  
SEGDIO1/VPULSE, respectively (pins 45 and 44). The pulses can also be output on OPT_TX pin 53  
(see OPT_TXE[1:0], I/O RAM 0x2456[3:2] for details).  
ADC MUX Frame  
MUX_DIV Conversions (MUX_DIV=4 is shown)  
Settle  
CK32  
150  
MUX_SYNC  
CE CODE  
WPULSE  
S0  
S1  
S2  
S3  
S4  
S5  
W_FIFO  
S0  
S1  
S2  
S3  
S4  
S5  
RST  
S0  
S1  
S2  
S3  
S4  
S5  
4*PLS_INTERVAL  
4*PLS_INTERVAL  
4*PLS_INTERVAL  
4*PLS_INTERVAL  
4*PLS_INTERVAL  
4*PLS_INTERVAL  
1. This example shows how the FIFO distributes 6 pulse generator updates over one MUX frame.  
2. If WPULSE is low longer than (2*PLS_MAXWIDTH+1) updates, WPULSE will be raised until the next  
low-going pulse begins.  
3. Only the WPULSE circuit is shown. The VARPULSE circuit behaves identically.  
4. All dimensions are in CK_FIR cycles (4.92MHz).  
5. If PLS_INTERVAL=0, FIFO does not perform delay.  
Figure 9. Pulse Generator FIFO Timing  
2.3.7 CE Functional Overview  
The ADC processes one sample per channel per multiplexer cycle. Figure 10 shows the timing of the  
samples taken during one multiplexer cycle with MUX_DIV[3:0] = 7 (I/O RAM 0x2100[7:4]).  
The number of samples processed during one accumulation cycle is controlled by the I/O RAM register  
SUM_SAMPS[12:0] (0x2107[4:0] and 0x2108[7:0]). The integration time for each energy output is:  
SUM_SAMPS[12:0] / 2184.53, where 2184.53 is the sample rate in Hz  
For example, SUM_SAMPS[12:0] = 2184 establishes 2184 multiplexer cycles per accumulation cycle or  
2184/2184.53 = 0.9998 seconds. After an accumulation cycle is completed, the XFER_BUSY interrupt  
signals to the MPU that accumulated data are available. The slight difference between the nominal length  
of the accumulation interval (1000 ms) and the actual length of 999.8 ms (0.025%) is accounted for in the  
CE code and is of no practical consequence.  
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© 2008–2011 Teridian Semiconductor Corporation  
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