71M6543F/H and 71M6543G/GH Data Sheet
Accumulator (ACC, A, SFR 0x E0):
ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The mnemonics
for accumulator-specific instructions refer to accumulator as A, not ACC.
B Register (SFR 0xF0):
The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register to
hold temporary data.
Program Status Word (PSW, SFR 0xD0):
This register contains various flags and control bits for the selection of the register banks (see Table 13).
Table 13: PSW Bit Functions (SFR 0xD0)
PSW Bit
Symbol
CV
Function
7
6
5
Carry flag.
AC
Auxiliary Carry flag for BCD operations.
F0
General purpose Flag 0 available for user.
F0 is not to be confused with the F0 flag in the CESTATUS register.
RS1
RS0
4
3
Register bank select control bits. The contents of RS1 and RS0 select the
working register bank:
Bank selected
Bank 0
Location
RS1/RS0
00
0x00 – 0x07
0x08 – 0x0F
0x10 – 0x17
0x18 – 0x1F
01
10
11
Bank 1
Bank 2
Bank 3
OV
–
2
1
0
Overflow flag.
User defined flag.
P
Parity flag, affected by hardware to indicate odd or even number of one bits in
the Accumulator, i.e. even parity.
Stack Pointer (SP, SFR 0x81):
The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before
PUSH and CALL instructions, causing the stack to begin at location 0x08.
Data Pointer:
The data pointers (DPTR and DPRT1) are 2 bytes wide. The lower part is DPL (SFR 0x82) and DPL1 (SFR
0x84), respectively. The highest is DPH (SFR 0x83) and DPH1 (SFR 0x85), respectively. The data pointers
can be loaded as two registers (e.g. MOV DPL,#data8). They are generally used to access external code
or data space (e.g. MOVC A,@A+DPTR or MOVX A,@DPTR respectively).
Program Counter:
The program counter (PC) is 2 bytes wide and initialized to 0x0000 after reset. This register is incremented
when fetching operation code or when operating on data from program memory.
Port Registers:
SEGDIO0 through SEGDIO15 are controlled by Special Function Registers P0, P1, P2, and P3 as shown
in Table 14. Above SEGDIO15, the LCD_SEGDIOn[ ] registers in I/O RAM are used. Since the direction
bits are contained in the upper nibble of each SFR Pn register and the DIO bits are contained in the lower
nibble, it is possible to configure the direction of a given DIO pin and set its output value with a single
write operation, thus facilitating the implementation of bit-banged interfaces. Writing a 1 to a DIO_DIR
bit configures the corresponding DIO as an output, while writing a 0 configures it as an input. Writing a 1
to a DIO bit causes the corresponding pin to be at high level (V3P3), while writing a 0 causes the
corresponding pin to be held at a low level (GND). See 2.5.10 Digital I/O for additional details.
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