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71M6543H 参数 Datasheet PDF下载

71M6543H图片预览
型号: 71M6543H
PDF下载: 下载PDF文件 查看货源
内容描述: 可选增益1或8的一个电流电能表计量芯片的补偿 [Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation]
分类和应用:
文件页数/大小: 157 页 / 2164 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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71M6543F/H and 71M6543G/GH Data Sheet  
6.4.5 Supply Current  
The supply currents provided in Table 95 below include only the current consumed by the 71M6543.  
Refer to the 71M6xxx Data Sheet for additional current required when using a 71M6x03 remote sensor.  
Table 95: Supply Current Performance Specifications  
Parameter  
Condition  
Device  
Min  
Typ  
Max  
Unit  
Polyphase: 4 Currents, 3 Voltages  
V3P3A = V3P3SYS = 3.3 V,  
MPU_DIV [2:0]= 3 (614 kHz MPU clock),  
71M6543F/H  
7.2  
8.5  
I1:  
V3P3A + V3P3SYS current, No Flash memory write,  
mA  
RTM_E=0, PRE_E=0, CE_E=1, ADC_E=1,  
ADC_DIV=0, MUX_DIV[3:0]=7,  
FIR_LEN[1:0]=1, PLL_FAST=1  
Normal Operation  
71M6543G/GH  
7.5  
8.8  
I1a:  
71M6543F/H  
6.4  
6.7  
7.3  
7.7  
Same as I1, except ADC_DIV=1, FIR_LEN=0  
V3P3A + V3P3SYS current,  
ADC Half Rate  
(ADC_DIV=1)  
mA  
mA  
mA  
71M6543G/GH  
I1b:  
71M6543F/H  
2.9  
3.0  
3.8  
3.9  
V3P3A + V3P3SYS current,  
Normal Operation  
PLL_FAST=0  
Same as I1, except PLL_FAST=0  
Same as I1, except PRE_E=1  
71M6543G/GH  
I1c:  
71M6543F/H  
7.3  
7.7  
8.7  
9.1  
V3P3A + V3P3SYS current,  
Normal Operation  
PRE_E=1  
71M6543G/GH  
I1d:  
71M6543F/H  
6.5  
6.9  
7.5  
7.9  
V3P3A + V3P3SYS current,  
Normal Operation  
PRE_E=1, ADC_DIV=1,  
FIR_LEN=0.  
Same as I1, except PRE_E=1, ADC_DIV=1,  
FIR_LEN=0.  
mA  
mA  
71M6543G/GH  
(see note 1)  
I1e:  
71M6543F/H  
3.0  
3.1  
3.9  
3.9  
V3P3A + V3P3SYS current,  
Normal Operation  
PLL_FAST=0, PRE_E=1.  
(see note 1)  
Same as I1, except PRE_E=1, PLL_FAST=0.  
71M6543G/GH  
Same as I1, except with variation of  
MPU_DIV[2:0].  
71M6543F/H  
0.4  
0.5  
0.6  
I2:  
mA/  
MHz  
V3P3A + V3P3SYS dynamic  
current  
IMPU_DIV=0 - IMPU_DIV=3  
4.3  
71M6543G/GH  
0.65  
VBAT current  
I3: MSN Mode  
I4: BRN Mode  
71M6543  
71M6543F/H  
71M6543G/GH  
71M6543  
-300  
0
300  
3.2  
3.5  
108  
36  
11  
nA  
mA  
mA  
nA  
µA  
µA  
µA  
nA  
CE_E=0  
2.4  
2.6  
0.4  
24  
3.0  
1.1  
0
I5: LCD Mode (ext. VLCD)  
I6: LCD Mode (boost, DAC)  
I7: LCD Mode (DAC)  
I8: LCD Mode (VBAT)  
I9: SLP Mode  
LCD_VMODE[1:0]=3, also see note 3  
LCD_VMODE[1:0]=2, also see notes 1, 2  
LCD_VMODE[1:0]=1, also see notes 1, 2  
LCD_VMODE[1:0]=0, also see notes 1, 2  
SLP Mode  
71M6543  
71M6543  
71M6543  
71M6543  
3.4  
+300  
-300  
-300  
VBAT_RTC current  
I10: MSN  
I11: BRN  
71M6543  
71M6543F/G  
71M6543G/GH  
71M6543  
0
300  
410  
420  
4.1  
1.7  
3.2  
nA  
nA  
nA  
µA  
µA  
µA  
240  
260  
1.8  
0.7  
1.5  
I12: LCD Mode  
I13: SLP Mode  
I14: SLP Mode (see note 1)  
LCD_VMODE[1:0]=2, also see note 3  
TA ≤ 25 °C  
TA = 85 °C  
71M6543  
71M6543  
I15:  
71M6543F/G  
7.1  
7.3  
8.7  
8.7  
Same as I1, except write Flash at maximum rate,  
CE_E=0, ADC_E=0.  
V3P3A + V3P3SYS current,  
Write Flash with ICE  
mA  
71M6543G/GH  
Notes:  
1.  
2.  
3.  
Guaranteed by design; not production tested.  
LCD_DAC[4:0]=5 (2.9V), LCD_CLK[1:0]=2, LCD_MODE[2:0]=6, all LCD_MAPn bits = 0.  
LCD_DAC[4:0]=5 (2.9V), LCD_CLK[1:0]=2, LCD_MODE[2:0]=6, LCD_BLANK=0, LCD_ON=1, all LCD_MAPn bits = 1 and VLCD pin = 3.3V.  
138  
© 2008–2011 Teridian Semiconductor Corporation  
v1.2  
 
 
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