71M6543F/H and 71M6543G/GH Data Sheet
Name
Location Rst Wk Dir Description
RMT2_E
RMT4_E
RMT6_E
2709[3]
2709[4]
2709[5]
0
0
R/W Enables the remote interface.
RMT_RD[15:8]
RMT_RD[7:0]
2602[7:0]
2603[7:0]
0
0
R
Response from remote read request.
RTCA_ADJ[6:0]
2504[6:0] 40 – R/W Register for analog RTC frequency adjustment.
Indicates that a count error has occurred in the RTC and that the time is not trustworthy.
This bit can be cleared by writing a 0.
RTC_FAIL
2890[4]
0
0
R/W
R/W
R/W
RTC_P[16:14]
RTC_P[13:6]
RTC_P[5:0]
RTC adjust. See 2.5.4 Real-Time Clock (RTC).
0x0FFBF ≤ RTC_P ≤ 0x10040
Note: RTC_P[16:0] and RTC_Q[1:0] form a single 19-bit RTC adjustment value.
289B[2:0]
289C[7:0]
289D[7:2]
4
0
0
4
0
0
RTC adjust. See 2.5.4 Real-Time Clock (RTC).
Note: RTC_P[16:0] and RTC_Q[1:0] form a single 19-bit RTC adjustment value.
RTC_Q[1:0]
289D[1:0]
0
0
Freezes the RTC shadow register so it is suitable for MPU reads. When RTC_RD is
read, it returns the status of the shadow register:
0 = up to date, 1 = frozen.
RTC_RD
2890[6]
0
0
R/W
R
RTC_SBSC[7:0]
RTC_TMIN[5:0]
2892[7:0]
289E[5:0]
–
0
–
–
Time remaining since the last 1 second boundary. LSB=1/128 second.
R/W The target minutes register. See RTC_THR below.
The target hours register. The RTC_T interrupt occurs when RTC_MIN [5:0] becomes
equal to RTC_TMIN[5:0] and RTC_HR[4:0] becomes equal to RTC_THR[4:0].
RTC_THR[4:0]
289F[4:0]
0
–
R/W
Freezes the RTC shadow register so it is suitable for MPU writes. When RTC_WR is
cleared, the contents of the shadow register are written to the RTC counter on the next
RTC clock (~1 kHz). When RTC_WR is read, it returns 1 as long as RTC_WR is set. It
RTC_WR
2890[7]
0
0
R/W
continues to return one until the RTC counter actually updates.
The RTC interface. These are the year, month, day, hour, minute and second parameters
for the RTC. The RTC is set by writing to these registers. Year 00 and all others divisible
by 4 are defined as a leap year.
RTC_SEC[5:0]
RTC_MIN[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
2893[5:0]
2894[5:0]
2895[4:0]
2896[2:0]
2897[4:0]
2898[3:0]
2899[7:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SEC 00 to 59
MIN 00 to 59
HR 00 to 23 (00=Midnight)
DAY 01 to 07 (01=Sunday)
DATE01 to 31
R/W
MO 01 to 12
YR
00 to 99
Each write operation to one of these registers must be preceded by a write to 0x20A0.
RTM_E
2106[1]
0
0
R/W Real Time Monitor enable. When 0, the RTM output is low.
© 2008–2011 Teridian Semiconductor Corporation
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