MV78100
Hardware Specifications
USB PHY PLL
SATA PHY PLL
The different MV78100 PLLs require dedicated quiet power supplies (AVDD/AVSS).
See the MV76100, MV78100, and MV78200 Design Guide for a detailed description of
these power supplies and required power filtering.
Note
The MV78100 clocking scheme is shown in Figure 3.
Figure 3: MV78100 Clocks
SheevaTM
Core
PCLK
M_CLK_OUT[2:0]/
M_CLK_OUTn[2:0]
HCLK
PCLK
PLL
DRAM
Controller
TCLK to all of
the chip units
CLK_25_SSC
TCLK PLL
TCLK_OUT
TCLK_IN
1:N
de-skew
PLL
CLK25_PT
USB PHY
PLL
CLK125
(GE) PLL
SATA
PHY PLL
PEX_0 100 MHz HCSL
PEX_1 100 MHz HCSL
PCI-E
PHYs
The MV78100 supports generation of PCLK, HCLK, and TCLK from a 25 MHz input clock
CLK25_SSC. This clock can be generated by a spread spectrum clock generator (SSCG) under the
following restrictions:
Spread does not exceed -0.5% of the maximum frequency.
The modulation frequency does not exceed 33 KHz.
The PLLs using this clock source track the spread characteristics of the input clock (meaning TCLK,
PCLK, HCLK, and M_CLK_OUT also become spread spectrum clocks).
There is a single PCLK PLL that generates PCLK (CPU clock), and HCLK (CPU bus clock which is
also DRAM clock). Both clocks are synchronous to each other (edge aligned), resulting in low
latency CPU to DRAM path (no synchronization required).
The CPU L2 cache clock (named XPCLK) runs relative to the CPU PCLK, with the ratio determined
by the reset configuration.
MV-S104552-U0 Rev. D
Page 42
Copyright © 2008 Marvell
Document Classification: Proprietary Information
December 6, 2008, Preliminary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
