LF3370
DEVICES INCORPORATED
High-Definition Video Format Converter
halfband filters to the data flowing
through the LF3370. A latched HIGH to
synchronizationisdesired. Therefore,
when there is a HIGH to LOW transition
FIGURE 8. INPUT BIAS
LOW transition on SYNC control signal is onSYNC, thefollowingisassumed:Cb
R3
R0
neededtoinitializethedevicetomarkthe
beginning of valid data.
will occur on the first LOW on SYNC that
islatched, Cbwilloccureverytwoclock
cyclesifinterleavedChromaispresented
to the input port B12-0, Cb will occur every
4 clock cycles if single channel 4:2:2
interleavedvideoispresentedtotheinput
port A12-0.
2
INBIAS1-0
In addition, if 4:2:2 interleaved video data
isdesiredforinputoroutput, aHIGHto
LOW transition on SYNC must be
registeredbyasimultaneousrisingedgeof
CLK and CLK/2. CLK/2 is an internal
clock that must be synchronized to CLK
13
13
13
13
From Input Demux
SYNC control signal is also used to
FIGURE 9. OUTPUT BIAS
by use of RESET only if the core is running synchronizetheinterpolation/decimation
athalftherateofCLK(seeRESET
discussio n and Figures 4 & 5).
outputdatafromtheHalf-BandFilterto
theOutputMultiplexer. Thissynchroniza-
tionisdoneautomatically.
R3
R0
2
OUTBIAS1-0
Furthermore,SYNCisusedtoidentifyone
interleaveddatasetfromanother. For
example,inthecaseofinterleaved
Chroma, Cb and Cr samples must be
properly demultiplexed and synchro-
nized for processing.
RESET
13
13
13
RESET should be used when initializing
the device for proper operation. It is used
to synchronize the LF3370 core clock to
the master clock. In the case that single
channel 4:2:2 interleaved video data is
desired either on the input or output, thus
using only one input or one output port
(not including Key data), the internal
clock rate will be half (CLK/2) of the
master clock rate (CLK). In this case,
RESET is needed to synchronize the rising
edge of CLK/2 to a known rising edge of
CLK (see Figure 4). For example, after
configuringtheLF3370andbefore
From Core
streaming valid data through the part, a
RESET event should be used to align the
clockedges(seeFigure4&5).
TodifferentiateaCbsamplefromCr,there
needs to be a HIGH to LOW transition on
SYNConthefirstCbsample(seeFigure4
&5);SYNCcanalsobetoggledonevery
Cbsampleforre-synchronization.
Furthermore, RESETwillclearHF0 and
HF1. A LOW state detected on RESET on a
rising edge of clock will clear flags HF0
and HF1 on the following rising edge of
clock. PleasenoteHBLANKshouldbe
In the case that Cb is the first valid data
word, SYNCmaybeusedonlyoncein
device initialization and kept low until re-
FIGURE 10.
HBLANK AND COUNTER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CLK
HBLANK
20-bit
COUNTER
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
HF
HF
0
1
A'12-0*
B'12-0*
C'12-0*
D'12-0*
DN
DN
DN
DN
HBLANK Word A
HBLANK Word B
HBLANK Word C
HBLANK Word D
DN+3
DN+3
DN+3
DN+3
DN+4
DN+4
DN+4
DN+4
DN+5
DN+5
DN+5
DN+5
DN+6
DN+6
DN+6
DN+6
DN+7
DN+7
DN+7
DN+7
DN+8
DN+8
DN+8
DN+8
DN+9
DN+9
DN+9
DN+9
DN+10
DN+10
DN+10
DN+10
DN+11
DN+11
DN+11
DN+11
HBLANK Word A
HBLANK Word B
HBLANK Word C
HBLANK Word D
*
Data values at output of Input LUT section
In this example, HF Count Value is set to 3 and HF
0
1
Count Value is set to 5
Video Imaging Products
03/13/2001–LDS.3370-F
8
LOGIC [ LOGIC DEVICES INCORPORATED ]
