LF3370
DEVICES INCORPORATED
High-Definition Video Format Converter
tant that unused input ports be set either
HIGH or LOW.
Output Multiplexer
The output multiplexer section can be
configured in various ways to accommo-
date the video system. Bits 2 and 3 of
Configuration Register 0 determines the
number of output channels that the
LF3370 will drive. Z
12-0
is the Key
channel output port; the Key channel
simply gets passed through the output
multiplexer with a latency that matches
the other three channels.
If three separate output channels of non-
interleaved video are desired, no multi-
plexing is performed. The three channels
are passed through the output multi-
plexer unmodified on the output ports
W
12-0
, X
12-0
, and Y
12-0
with a delay of 2
CLK cycles. For this operation, bits 2 and
3 must both be set to 1 in Configuration
Register 0 (see Table 5).
If one channel of non-interleaved video
(i.e., Luma) and one channel of inter-
leaved video (i.e., Chroma) is desired (see
Figure 6), non-interleaved video will be
driven to the output port W
12-0
and
interleaved video will be driven to the
output port X
12-0
with a delay of 2 CLK
cycles. For this operation, bit 2 must be set
to 0 and bit 3 must be set to 1 in Configu-
ration Register 0 (see Table 5).
If 4:2:2 interleaved video on one port is
desired (see Figure 7), interleaved video
will be driven to the output port W
12-0
with a delay of 4 CLK cycles. For this
operation, bit 2 must be set to 1 and bit 3
must be set to 0 in Configuration Register 0
(see Table 5).
All output multiplexing operations are
initiated by the latched HIGH to LOW
transitions of SYNC which synchronizes
the multiplexed output data to the LF3370
core (see SYNC discussion).
SYNC
SYNC control signal is required to
properly synchronize the input
demultiplexer, output multiplexer, and
and interleaved video is presented to input
port B
12-0
(i.e., Chroma). The input
demultiplexer, in this case, separates video
data on B
12-0
and outputs two channels of
separated video into the LF3370 core with
a delay of 4 CLK cycles. For this operation,
bit 0 must be set to 0 and bit 1 must be set to
1 in Configuration Register 0 (see Table 5).
If 4:2:2 video data is on one channel
interleaved (see Figure 5), it is assumed
that interleaved video is presented to input
port A
12-0
. The input demultiplexer, in
this case, separates video data on A
12-0
and outputs three channels of separated
video into the LF3370 core with a delay of
5 CLK cycles. In this case, the core will
run at half of the CLK rate and valid data
will be output at at half of the CLK rate.
For this operation, bit 0 must be set to 1
and bit 1 must be set to 0 in Configuration
Register 0 (see Table 5).
All input demultiplexing operations are
controlled by the latched HIGH to LOW
transitions of SYNC which synchronizes
the LF3370 core to the multiplexed input
data (see SYNC discussion). It is impor-
F
IGURE
6. O
UTPUTTING
4:2:2:4 (I
NTERLEAVED
C
HROMA ON
C
HANNEL
X)
CLK
W
12-0
X
12-0
Y
0 (Output SYNC)*
Z
12-0
K
0
K
1
K
2
K
3
K
4
K
5
K
6
K
7
K
8
K
9
K
10
K
11
K
12
K
13
K
14
K
15
K
16
K
17
Y
0
CB
0
Y
1
CR
0
Y
2
CB
2
Y
3
CR
2
Y
4
CB
4
Y
5
CR
4
Y
6
CB
6
Y
7
CR
6
Y
8
CB
8
Y
9
CR
8
Y
10
CB
10
Y
11
CR
10
Y
12
CB
12
Y
13
CR
12
Y
14
CB
14
Y
15
CR
14
Y
16
CB
16
Y
17
CR
16
*
There will be a HIGH to LOW transition on every Cb sample
F
IGURE
7. O
UTPUTTING
4:2:2:4 (I
NTERLEAVED
L
UMA
/C
HROMA ON
C
HANNEL
W)
CLK
W
12-0
Y
0 (Output SYNC)*
Z
12-0
K
0
K
1
K
2
K
3
K
4
K
5
K
6
K
7
K
8
CB
0
Y
0
CR
0
Y
1
CB
2
Y
2
CR
2
Y
3
CB
4
Y
4
CR
4
Y
5
CB
6
Y
6
CR
6
Y
7
CR
8
Y
8
*
There will be a HIGH to LOW transition on every Cb sample
Video Imaging Products
7
03/13/2001–LDS.3370-F
LOGIC [ LOGIC DEVICES INCORPORATED ]
