LF3370
DEVICES INCORPORATED
High-Definition Video Format Converter
HF1/HF0 — HBlank Flags
HBLANK —HorizontalBlankingControl
SIGNALDEFINITIONS
Power
HF1 and HF0 are two general purpose
flags used to indicate when a 20-bit
counter reaches its user-defined
terminal count; a HIGH to LOW
transition of HBLANK and/or RESET
will reset the flags.
HBLANK is used for data replacement
correspondingtouser-selectable
blanking levels. A HIGH to LOW
transition resets the counter and the
HFx flags.This signal is latched on the
risingedgeofCLK.
VCC andGND
+3.3 V power supply. All power pins
mustbeconnected.
Clock
Controls
CLK — Master Clock
INBIAS1-0 — Input Bias Control
LD — Configuration Load
The rising edge of CLK strobes all
enabled registers. To guarantee data
integrity, a minimum of 25KHz must
bemaintained.
INBIAS1-0 determines which of the
four user-programmable Input Bias
registers are used to sum with the
input data. These pins are latched on
the rising edge of CLK.
When LD is LOW, data on CF12-0 is
latched into the LF3370 LF InterfaceTM
on the rising edge of CLK. When LD
is HIGH, data is not loaded into
the LF InterfaceTM. When enabling
the LF InterfaceTM for data input, a
Inputs
OUTBIAS1-0 —OutputBias Control
A12-0, B12-0, C12-0, D12-0 — Data Inputs latched HIGH to LOW transition of
OUTBIAS1-0 determines which of the
four user-programmable Output Bias
registers are used to sum with the
output data.These pins are latched on
the rising edge of CLK.
LD is required in order for the input
A12-0, B12-0, C12-0, and D12-0 are the
circuitry to function properly.
13-bit registered data input ports.
Therefore, LD must be set HIGH
Data is latched on the rising edge of
immediately after power up to
CLK.
ensure proper operation of the input
circuitry.
CF12-0 — Coefficient Input
RSL1-0 — Round/Select/Limit Control
SYNC — Synchronization for data alignment
CF12-0 is used to address and load
Colorspace/Key Scaler coefficient
banks, Round/Select/Limit registers,
and Configuration registers. Data
present on CF12-0 is latched into the
LF InterfaceTM on the rising edge of
CLK when LD is LOW.
RSL1-0 determines which of the user-
programmable Round/Select/Limit
registers (RSL registers) are used in
the RSL circuitry. A value of 00 on
RSL1-0 selects RSL register 0. A value
of 01 selects RSL register 1 and so on.
RSL1-0 is latched on the rising edge of
CLK.
SYNC control signal is required to
properly synchronize the input
demultiplexer, output multiplexer,
and halfband filters to the data
flowing through the LF3370. A
latched HIGH to LOW transition tells
the core which sample corresponds to
aCb/Crsampleforproperde-multi-
CA1-0 — Coefficient Address
plexing and multiplexing. This signal OE — Output Enable
CA1-0 determines which of the four
user-programmable Colorspace/Key
Scaler Coefficients are used.
will also synchronize the half-band
When OE is LOW, W12-0, X12-0, Y12-0,
filters into a decimation/interpolation
sequence. This signal is latched on the
risingedgeofCLK.
and Z12-0 are enabled for output.
When OE is HIGH, W12-0, X12-0, Y12-0,
and Z12-0 are placed in a high-
impedance state.
Outputs
W12-0 , X12-0 , Y12-0 , Z12-0 — Data Outputs
DATAPASS—DatapassMode
PAUSE — LF InterfaceTM Pause
W12-0, X12-0, Y12-0, and Z12-0 are the
13-bitregistereddataoutputports.
Outputs are updated on the rising
edgeofCLK.
DATAPASS is used to place the
LF3370 in a mode of operation that
allows the user to pass data through
the core (Input/Output Bias Adders,
LUTs, Hafband Interpolator/
Decimator, Colorspace/Key Scaler)
without any processing. This signal is
latched on the rising edge of CLK.
When PAUSE is HIGH, the LF3370
LF InterfaceTM loading sequence is
halted until PAUSE is returned to a
LOW state. This effectively allows
the user to load coefficients and
control registers at a slower rate than
the master clock. This pin is latched
Video Imaging Products
03/13/2001–LDS.3370-F
4
LOGIC [ LOGIC DEVICES INCORPORATED ]
