LF3370
DEVICES INCORPORATED
High-Definition Video Format Converter
corresponding output peak is 35 clock
cycles.
FIGURE 13. RSL CIRCUITRY
UL3
LL3
UL0
The input/output formats are always in
R3
R0
S3
S0
LL0
two’s complement format as shown in
Figure 3. In Interpolate Mode, the gain of
the Half-Band Filter is halved (due to half
of the input samples being padded with
zeros). A right shifted Select window is
2
RSL1-0
20
13
13
20
20
13
13
13
From Core
ROUND
SELECT
LIMIT
required to maintain an overall filter gain
of 1. It is possible that ringing on the
filter’s output could cause the high order
bit(bitF18inFigure3-InterpolateFilter
OutputBitWeighting)tobecomeHIGH. If
a right shifted Select window is used, this
F18bitbecomesthesignbitoftheSelected
window – and the output is erroneously
considerednegative. Toensurethatno
overflow conditions occur, an internal
Limiter within each Half-Band Filter
TABLE 2. SELECT FORMATS
SLCT1-0
S12 S11 S10 S9
F16 F15 F14 F13 F12 F11 F10 F9
F17 F16 F15 F14 F13 F12 F11 F10 F9
S8
S7
S6
S5
S4
S3
S2
F6
F7
F8
S1
S0
F4
F5
F6
F7
00
F8
F7
F8
F5
F6
F7
F8
01
10
F18 F17 F16 F15 F14 F13 F12 F11 F10 F9
monitorsitsoutput. DuringInterpolate
mode,thisLimiterclampstheoutputword
to3FFFFH(20-bitmaximumpositivevalue
11
F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9
plierbysettingbit4inConfiguration
Register 0 (see Table 5). The maximum
input and output clock rate this section
can operate at is the CLK rate. The total
internal pipeline latency from the input to input samples.
the output of this section (including RSL
rateistheCLKrate. Toperformdecima-
tion, the output data rate of this section
will be half of the input data rate. One
output sample is obtained for every two
)2)orC0000H(20-bitmaximumnegative
value)2)ifapositiveornegativeoverflow
occursrespectively. Theinternal24-bitsof
theHalf-BandFilteraretruncatedto20-
bits and then passed to the Round section
oftheRSLcircuitry;seeRSLsectionfor
further details. This section is fully
bypassablebyuseofprogrammable
delays (see Bypass Options section for
furtherdetails).
Once an impulse is clocked into the Half-
BandFiltersection, the55-valueoutput
response begins after 8 clock cycles and
circuitry) as shown in Figure 12 is 6 cycles.
Toperforminterpolation,theinputdata
rate of this section will be half of CLK rate. ends after 62 clock cycles. The pipeline
Please note the maximum output data latency from the input of an impulse to its
FIGURE 14. FREQUENCY RESPONSE OF FILTER
Look-UpTable
0
–10
–20
–30
–40
–50
–60
–70
–80
ThreeoptionalprogrammableInput/
Output 1K x 13-bit LUTs have been
provided for Channels A, B, and C for
various uses such as Gamma Correction.
There are NOT actually two LUTs per
channel as shown in Figures 1 and 2; only
one LUT per channel can be selected for
use at any given time. The latency
through a LUT section is 2 cycles. This
latency is present on the datapath regard-
less of whether the LUT is in use or not.
When using a LUT, the appropriate
addressed value will be passed as an
0
0.1ƒS
0.2ƒS
0.3ƒS
0.4ƒS
0.5ƒS
FREQUENCY (NORMALIZED)
Video Imaging Products
03/13/2001–LDS.3370-F
11
LOGIC [ LOGIC DEVICES INCORPORATED ]
