LF3370
DEVICES INCORPORATED
High-Definition Video Format Converter
reset. HF0 and HF1 count value register
loading is discussed in the LF Interface™.
Please note, using HBLANK is the
programmedandselectedbyCA1-0.A
value of 00 on CA1-0 selects Coefficient Set
0 on each of the 9 coefficient banks. A
Thetotalpipelinelatencyfromtheinputof
theKeyScalertotheoutputoftheRSL
Circuitry is 6 CLK cycles and new output
recommendedwayofclearingHF0 and
HF1 flags but they can be cleared by
value of 01 selects Coefficient Set 1 and so data is subsequently available every clock
on. CA1-0 may be changed every clock cycle thereafter. If scaling is not desired,
RESET,normallyperformedduringdevice cycle if desired. Coefficient bank loading is load and select a Key Scaler Coefficient
initialization. RESET will not reset the
counter.
discussedintheLFInterface™.
value of 1 (see also First Operation Select in
the Bypass Options duscussion).
Thetotalpipelinelatencyfromtheinputof
theMatrixMultipliertotheoutputofthe
RSL Circuitry is 6 CLK cycles and new
output data is subsequently available
every clock cycle thereafter.
Input/OutputBiasAdder
Half-BandFilter
TheprogrammableInput/OutputBias
Adders can be used to subtract or add a
13-bit offset to the data. Input and output
data formats for the two sections are
shown in Figure 3. By using INBIAS1-0,
theusermayselectoneoffourpro-
grammed Input Bias Adder values (see
Figure 8). By using OUTBIAS1-0, the user
may select one of four programmed
Output Bias Adder values (see Figure 9).
A value of 00 on INBIAS1-0/OUTBIAS1-0
selects Input/Output Bias Adder Register
0. A value of 01 selects Input/Output
Bias Adder Register 1 and so on.
INBIAS1-0/OUTBIAS1-0 may be changed
every clock cycle if desired. If a bias is not
desired, then bits 11 & 12 of Configuration
Register 1 can be set up to independently
disable the input and output bias values.
Thus, effectively zeroing the function.
The total pipeline latency from the input
to the output for each of the two sections
is one CLK cycle. Input/Output Bias
Adder Register loading is discussed in the
LF Interface™ section.
There are two internal Half-Band filters in
the LF3370. These Half-Band filters can
either interpolate, decimate, or pass
through data found on channel B and
channel C. Data on channel A and
channel D in this section pass through a
programmable127x13-bitdelay(see
Bypass Section). The filter section (as
show in Figure 12) is a fixed-coefficient,
linear-phase half-band (low-pass)
If matrix multiplication is not desired,
using the appropriate combination of
coefficientvalueswhilekeepinginmind
bitweighting,anidentitymatrixmaybe
set up to bypass the Matrix Multiplier
section (see also First Operation Select in
the Bypass Options discussion).
interpolating/decimating digital filter.
The filter in this section is a 55-tap
KeyScaler
transversal FIR with 13-bit coefficients as
shown in Table 3. The frequency re-
sponse (Figure 14) is in full compliance
with SMPTE 260M. This section can be
configured for 2:1 interpolation, 1:2
decimation, or pass-through mode by
setting bits 5-8 in Configuration Register 0
(see Table 5). This section can also be
placed before or after the matrix multi-
The Key channel is equiped with a 13 x 13-
bitKeyScaler(seeFigure11)producinga
truncated 20-bit output which is then fed
into the RSL circuitry (see Figure 13). Up to
fouruser-defined13-bitcoefficientscanbe
programmedandselectedbyCA1-0.
Input/Outputformatsareshownin
Figure3.
FIGURE 12. 1:2 INTERPOLATION / 2:1 DECIMATION HALF-BAND FILTERS
VARIABLE LENGTH BYPASS DELAY
127 x 13-Bit
13
B'
3 x 3 Matrix Multiplier
Processing almost 550 million colors, three
simultaneous 13-bit input and output
channels are utilized to implement a 3 x 3-
matrix multiplication (triple dot product).
Each truncated 20-bit output is the sum of
all three input words multiplied by the
appropriate coefficients (see Figure 11).
These outputs are then fed into the RSL
circuitry (see Figure 13). Input/Output
formats are shown in Figure 3.
13
55-TAP
FIR
FILTER
INTERPOLATION
CIRCUIT
DECIMATION
CIRCUIT
B
R
S L
CONFIGURATION / CONTROL
REGISTERS
13
55-TAP
FIR
FILTER
INTERPOLATION
CIRCUIT
DECIMATION
CIRCUIT
C
R
S L
13
C'
For each of the nine multipliers, up to four
user-defined 13-bit coefficients can be
VARIABLE LENGTH BYPASS DELAY
127 x 13-Bit
Video Imaging Products
03/13/2001–LDS.3370-F
10
LOGIC [ LOGIC DEVICES INCORPORATED ]
