LTC1699 Series
W U
W
TI I G DIAGRA S
Timing for SMBus Interface
t
BUF
SDA
SCL
t
t
HD:STA
HD:STA
t
t
f
r
t
LOW
t
t
t
HIGH
SU:STO
SU:STA
1699 TD02
t
t
SU:DAT
HD:DAT
STOP
START
START
STOP
CLK_ON, IO_ON, CLK_ON, PGOOD TIMING
P
P
SCL
SDA
2nd ON
PROTOCOL
2nd OFF
PROTOCOL
STOP
SMBON 1.3V
DCON 1.3V
SEL 1.3V
CPU_ON
t
PH
t
t
t
t
SPL
VL
PL
1.3V
IO_ON
CLK_ON
t
t
PGL
PGL
PPL
t
VH
PGOOD
VRON
0.7V
t
PGL
t
VPL
t
t
SSH
SSL
V
V
MAX
MIN
0V
90%
V
SENSE
10%
(V
= 0.8V)
REF
0V
NOTE: TIMING RELATIVE TO THE STOP BIT (P) IS MEASURED FROM THE RISING EDGE OF SDA
SEE TABLE 1 FOR V AND V SENSE VOLTAGES
1699 TD03
MIN
MAX
9
Linear [ Linear ]
