LTC2943
APPLICATIONS INFORMATION
2
The reduction of the impact of the offset in LTC2943 can
beexplainedbyitsintegrationschemedepictedinFigure2.
While positive offset accelerates the up ramping of the
integrator output from REFLO to REFHI, it slows the down
ramping from REFHI to REFLO thus the effect is largely
canceled as depicted below.
I C Protocol
2
The LTC2943 uses an I C/SMBus-compatible 2-wire
interface supporting multiple devices on a single bus.
Connected devices can only pull the bus lines low and
mustneverdrivethebushigh.Thebuswiresareexternally
connected to a positive supply voltage via current sources
or pull-up resistors. When the bus is idle, all bus lines are
high. Data on the I C bus can be transferred at rates of
up to 100kbit/s in standard mode and up to 400kbit/s in
fast mode.
INTEGRATOR
OUTPUT
2
REFHI
WITHOUT OFFSET
WITH OFFSET
2
Each device on the I C/SMbus is recognized by a unique
REFLO
address stored in that device and can operate as either a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
can also be classified as masters or slaves when perform-
ing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals to
permitthattransfer.Atthesametimeanydeviceaddressed
is considered a slave. The LTC2943 always acts as a slave.
TIME
FASTER
UP RAMPING
SLOWER
DOWN RAMPING
2943 F0B
For input signals with an absolute value smaller than the
offset of the internal op amp, the LTC2943 stops integrat-
ing and does not integrate its own offset.
Figure 4 shows an overview of the data transmission on
2
I C/SMBus Interface
2
the I C bus.
The LTC2943 communicates with a bus master using
2
Start and Stop Conditions
a 2-wire interface compatible with I C and SMBus. The
2
7-bit hard coded I C address of the LTC2943 is 1100100.
When the bus is idle, both SCL and SDA must be high. A
bus master signals the beginning of a transmission with
a START condition by transitioning SDA from high to low
while SCL is high. When the master has finished com-
municating with the slave, it issues a STOP condition by
The LTC2943 is a slave only device. The serial clock line
(SCL) is input only while the serial data line (SDA) is
bidirectional. The device supports I C standard and fast
mode. For more details refer to the I C Protocol section.
2
2
SDA
SCL
a6 - a0
b7 - b0
DATA
b7 - b0
1 - 7
8
9
1 - 7
8
9
1 - 7
8
9
S
P
ADDRESS
R/W
ACK
ACK
DATA
ACK
START
CONDITION
STOP
CONDITION
2943 F04
Figure 4. Data Transfer Over I2C or SMBus
2943fa
15
For more information www.linear.com/LTC2943
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