LTC1400
PI FU CTIO S
V
CC
(Pin 1):
Positive Supply, 5V. Bypass to GND (10μF
tantalum in parallel with 0.1μF ceramic).
A
IN
(Pin 2):
Analog Input. 0V to 4.096V (Unipolar), ±2.048V
(Bipolar).
V
REF
(Pin 3):
2.42V Reference Output. Bypass to GND
(10μF tantalum in parallel with 0.1μF ceramic).
GND (Pin 4):
Ground. GND should be tied directly to an
analog ground plane.
D
OUT
(Pin 5):
The A/D conversion result is shifted out
from this pin.
A
IN
V
REF
2.42V REF
CLK
CONV
CONTROL
LOGIC
SUCCESSIVE APPROXIMATION
REGISTER/PARALLEL TO
SERIAL CONVERTER
TEST CIRCUITS
5V
3k
D
OUT
3k
C
LOAD
D
OUT
C
LOAD
Hi-Z TO V
OH
V
OL
TO V
OH
V
OH
TO Hi-Z
6
W
FU CTIO AL BLOCK DIAGRA
U
U
U
U
U
CLK (Pin 6):
Clock. This clock synchronizes the serial data
transfer. A minimum CLK pulse of 50ns will cause the ADC
to wake up from Nap or Sleep mode.
CONV (Pin 7):
Conversion Start Signal. This active high
signal starts a conversion on its rising edge. Keeping CLK
low and pulsing CONV two/four times will put the ADC
into Nap/Sleep mode.
V
SS
(Pin 8):
Negative Supply. –5V for bipolar operation.
Bypass to GND with 0.1μF ceramic. V
SS
should be tied to
GND for unipolar operation.
C
SAMPLE
ZEROING SWITCH
V
CC
GND
V
SS
12-BIT CAPACITIVE DAC
COMP
12
D
OUT
1400 BD01
Hi-Z TO V
OL
V
OH
TO V
OL
V
OL
TO Hi-Z
1400 TC01
1400fa
LINER [ LINEAR TECHNOLOGY ]
