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MACH215-12JC 参数 Datasheet PDF下载

MACH215-12JC图片预览
型号: MACH215-12JC
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度EE CMOS可编程逻辑 [High-Density EE CMOS Programmable Logic]
分类和应用: 可编程逻辑器件输入元件时钟
文件页数/大小: 30 页 / 243 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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CAPACITANCE (Note 1)  
Parameter  
Symbol  
Parameter Description  
Test Conditions  
VIN = 2.0 V  
Typ  
6
Unit  
pF  
CIN  
Input Capacitance  
Output Capacitance  
VCC = 5.0 V, TA = 25°C,  
COUT  
VOUT= 2.0 V  
f = 1 MHz  
8
pF  
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)  
-14  
-18  
-24  
Parameter  
Symbol  
Parameter Description  
Min Max Min Max Min Max Unit  
tPD  
Input, I/O, or Feedback to Combinatorial Output  
(Note 3)  
14.5  
18  
24  
ns  
D-type  
T-type  
6
7.5  
6
7.5  
8.5  
7.5  
10  
11  
10  
ns  
ns  
ns  
ns  
ns  
Setup Time from Input, I/O, or  
Feedback to Product Term Clock  
tSA  
tHA  
Register Data Hold Time Using Product Term Clock  
Product Term Clock to Output (Note 3)  
tCOA  
tWLA  
17  
22  
26.5  
LOW  
10  
10  
42  
40  
47  
44  
50  
8.5  
10  
0
11  
11  
15  
15  
Product Term, Clock Width  
tWHA  
HIGH  
D-type  
T-type  
D-type  
T-type  
ns  
Maximum  
Frequency  
33  
26.5  
25.5  
28.5  
27.5  
33  
MHz  
MHz  
MHz  
MHz  
MHz  
ns  
External Feedback 1/(tSA + tCOA)  
32  
Using  
36  
Product  
Term  
Clock  
(Note 1)  
fMAXS  
Internal Feedback (fCNTA)  
No Feedback 1/(tWLA+ tWHA)  
34.5  
44.5  
12  
D-type  
T-type  
16  
Setup Time from Input, I/O,  
or Feedback to Global Clock  
tSS  
13.5  
0
17  
ns  
tHS  
Register Data Hold Time Using Global Clock  
Global Clock to Output (Note 3)  
0
ns  
tCOS  
tWLS  
tWHS  
10  
12  
14.5  
ns  
LOW  
7.5  
7.5  
7.5  
7.5  
40  
10  
10  
ns  
Global Clock Width  
Maximum  
HIGH  
D-type  
T-type  
D-type  
T-type  
ns  
53  
32  
MHz  
External Feedback 1/(tSS + tCOS)  
Frequency  
50  
38  
30.5  
40  
MHz  
MHz  
MHz  
MHz  
Using  
fMAXS  
66.5  
61.5  
66.5  
53  
Global  
Clock  
Internal Feedback (fCNTS)  
50  
38  
(Note 1)  
66.5  
50  
No Feedback  
1/(tWLS+ tWHS)  
Setup Time from Input, I/O,  
or Feedback to Product Term Gate  
Latch Data Hold Time Using Product Term Clock  
tSLA  
6
6
7.5  
7.5  
10  
10  
ns  
tHLA  
tGOA  
tGWA  
ns  
ns  
ns  
Product Term Gate to Output (Note 3)  
19.5  
12  
23  
26.5  
14.5  
Product Term Gate Width LOW (for LOW transparent)  
or HIGH (for HIGH transparent)  
10  
11  
14.5  
tSLS  
tHLS  
tGOS  
tGWS  
Setup Time from Input, I/O, or Feedback to Global Gate  
Latch Data Hold Time Using Global Gate  
Gate to Output (Note 3)  
8.5  
0
12  
0
16  
0
ns  
ns  
ns  
ns  
13.5  
Global Gate Width LOW (for LOW transparent)  
or HIGH (for HIGH transparent)  
7.5  
7.5  
10  
16  
MACH215-14/18/24 (Ind)  
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