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MACH215-12JC 参数 Datasheet PDF下载

MACH215-12JC图片预览
型号: MACH215-12JC
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度EE CMOS可编程逻辑 [High-Density EE CMOS Programmable Logic]
分类和应用: 可编程逻辑器件输入元件时钟
文件页数/大小: 30 页 / 243 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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CAPACITANCE (Note 1)  
Parameter  
Symbol  
Parameter Description  
Test Conditions  
VIN = 2.0 V  
Typ  
6
Unit  
pF  
CIN  
Input Capacitance  
Output Capacitance  
VCC = 5.0 V, TA = 25°C,  
COUT  
VOUT = 2.0 V  
f = 1 MHz  
8
pF  
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)  
-12  
-15  
-20  
Parameter  
Symbol  
Parameter Description  
Min Max Min Max Min Max Unit  
tPD  
tSA  
Input, I/O, or Feedback to Combinatorial Output (Note 3)  
3
5
6
12  
3
6
7
15  
3
8
9
20  
22  
ns  
ns  
ns  
D-type  
Setup Time from Input, I/O, or  
Feedback to Product Term Clock  
T-type  
tHA  
Register Data Hold Time Using Product Term Clock  
Product Term Clock to Output (Note 3)  
5
4
8
6
4
9
8
4
ns  
ns  
ns  
tCOA  
tWLA  
14  
18  
LOW  
12  
Product Term, Clock Width  
tWHA  
HIGH  
D-type  
T-type  
D-type  
T-type  
8
9
12  
33.3  
32.2  
35.7  
34.5  
41.7  
13  
ns  
MHz  
MHz  
MHz  
MHz  
MHz  
ns  
Maximum  
Frequency  
Using  
Product  
Term  
Clock  
52.6  
50  
41.7  
40  
External Feedback 1/(tSA + tCOA  
)
58.8  
55.6  
62.5  
7
45.5  
43.5  
55.6  
10  
fMAXA  
Internal Feedback (fCNTA  
)
No Feedback 1/(tWLA + tWHA  
)
(Note 1)  
D-type  
T-type  
Setup Time from Input, I/O,  
or Feedback to Global Clock  
tSS  
8
11  
14  
ns  
tHS  
Register Data Hold Time Using Global Clock  
Global Clock to Output (Note 3)  
0
0
0
ns  
tCOS  
tWLS  
tWHS  
2
8
2
10  
2
12  
ns  
LOW  
6
6
8
ns  
Global Clock Width  
HIGH  
D-type  
T-type  
D-type  
T-type  
6
6
8
ns  
66.7  
62.5  
83.3  
76.9  
83.3  
50  
40  
MHz  
MHz  
MHz  
MHz  
MHz  
Maximum  
Frequency  
Using  
External Feedback 1/(tSS + tCOS  
)
47.6  
66.6  
62.5  
83.3  
38.5  
50  
fMAXS  
Global  
Clock  
Internal Feedback (fCNTS  
)
47.6  
62.5  
(Note 1)  
No Feedback 1/(tWLS + tWHS  
)
Setup Time from Input, I/O,  
or Feedback to Product Term Gate  
tSLA  
5
5
6
6
8
8
ns  
tHLA  
tGOA  
tGWA  
Latch Data Hold Time Using Product Term Clock  
Product Term Gate to Output (Note 3)  
ns  
ns  
ns  
16  
10  
19  
11  
22  
12  
Product Term Gate Width LOW (for LOW transparent)  
or HIGH (for HIGH transparent)  
8
9
12  
tSLS  
tHLS  
tGOS  
tGWS  
Setup Time from Input, I/O, or Feedback to Global Gate  
Latch Data Hold Time Using Global Gate  
Gate to Output (Note 3)  
7
0
10  
0
13  
0
ns  
ns  
ns  
ns  
Global Gate Width LOW (for LOW transparent)  
or HIGH (for HIGH transparent)  
6
6
8
13  
MACH215-12/15/20 (Com’l)