n
From Logic
Allocator
n
To I/O
Cell
From Logic
Allocator
To I/O
Cell
To Switch
Matrix
To Switch
Matrix
a. Combinatorial, Active High
b. Combinatorial, Active Low
Individual
Preset
Individual
Preset
From Logic
Allocator
From Logic
Allocator
n
n
AP
AR
AP
AR
D
Q
D
Q
To I/O
Cell
To I/O
Cell
CLK0
CLK0
Individual
Clock
Individual
Clock
Individual
Preset
Individual
Preset
To Switch
Matrix
To Switch
Matrix
c. D-type Register, Active High
d. D-type Register, Active Low
Individual
Preset
Individual
Preset
From Logic
Allocator
From Logic
Allocator
n
n
AP
AR
AP
AR
T
Q
T
Q
To I/O
Cell
To I/O
Cell
CLK0
CLK0
Individual
Clock
Individual
Clock
Individual
Preset
Individual
Preset
To Switch
Matrix
To Switch
Matrix
f. T-type Register, Active Low
e. T-type Register, Active High
Individual
Individual
Preset
Preset
From Logic
Allocator
From Logic
Allocator
n
n
AP
AR
AP
AR
L
Q
L
Q
To I/O
Cell
To I/O
Cell
CLK0
CLK0
G
G
Individual
Clock
Individual
Clock
Individual
Preset
Individual
Preset
To Switch
Matrix
To Switch
Matrix
h. Latch, Active Low
g. Latch, Active High
16751E-6
Figure 4. Output Macrocell Configurations
MACH215-12/15/20
10
LATTICE [ LATTICE SEMICONDUCTOR ]
