Table 1. Logic Allocation
FUNCTIONAL DESCRIPTION
The MACH215 consists of four asynchronous PAL
blocks connected by a switch matrix. There are 32 I/O
pins and 4 dedicated input pins feeding the switch
matrix. These signals are distributed to the four PAL
blocks for efficient design implementation. There are
also two additional global clock pins that can be used as
dedicated inputs. This device provides two kinds of
macrocell: output macrocells and input macrocells. This
adds greater logic density without affecting the number
of pins.
Available
Clusters
Output Macrocell
M0
M1
M2
M3
M4
M5
M6
M7
C0, C1
C0, C1, C2
C1, C2, C3
C2, C3, C4
C3, C4, C5
C4, C5, C6
C5, C6, C7
C6, C7
The PAL Blocks
Each PAL block in the MACH215 (Figure 1) contains a
64-product-term array, a logic allocator, 8 output
macrocells, 8 input macrocells, and 8 I/O cells. The
switch matrix feeds each PAL block with 22 inputs. This
makes the PAL block look effectively like an independ-
ent “PAL22RA8” with 8 input macrocells. All flip-flops
within the device can operate independently.
The Macrocell
There are two types of macrocell in the MACH215:
output macrocells and input macrocells. The output
macrocell takes the logic of the device and provides it to
I/O pins and/or provides feedback for additional logic
generation. The input macrocell allows I/O pins to be
configured as registered or latched inputs.
The Switch Matrix
The MACH215 switch matrix is fed by the inputs and
feedback signals from the PAL blocks. Each PAL block
provides 16 internal feedback signals and 8 I/O
feedback signals. The switch matrix distributes these
signals back to the PAL blocks in an efficient manner
that also provides for high performance. The design
software automatically configures the switch matrix
when fitting a design into the device.
The output macrocell (Figure 3) can generate regis-
tered or combinatorial outputs. In addition, a transpar-
ent-low latched configuration is provided. If used, the
register can be configured as a T-type or a D-type
flip-flop. Register and latch functionality is defined in
Table 2. Programmable polarity and the T-type flip-flop
both give the software a way to minimize the number of
product terms needed. These choices can be made
automatically by the software when it fits the design into
the device.
The Product-term Array
The MACH215 product-term array consists of 32
product terms for logic use and 32 product terms for
generating macrocell control signals.
Table 2. Register/Latch Operation
Configuration
D/T
CLK/LE*
Q+
The Logic Allocator
D-Register
X
0
1
0, 1, ↓ (↑)
↑ (↓)
↑ (↓)
Q
0
1
The logic allocator in the MACH215 (Figure 2) takes the
32 logic product terms and allocates them to the 16
macrocells as needed. Each macrocell can be driven by
up to 12 product terms. The design software automati-
cally configures the logic allocator when fitting the
design into the device.
T-Register
Latch
X
0
1
0, 1, ↓ (↑)
↑ (↓)
↑ (↓)
Q
Q
Q
X
0
1
1 (0)
0 (1)
0 (1)
Q
0
1
Table 1 illustrates which product term clusters are
available to each macrocell within a PAL block. Refer to
Figure 1 for cluster and macrocell numbers.
*Polarity of CLK/LE can be programmed.
6
MACH215-12/15/20
LATTICE [ LATTICE SEMICONDUCTOR ]
