Architecture
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Figure 2-32. DQS Local Bus.
PIO
Delay
Control
Bus
DDR
Datain
PAD
sysIO
Buffer
Input
Register Block
( 5 Flip Flops)
Polarity
Control
Bus
To Sync.
Reg.
DI
GSR
CLKI
CEI
DQS
Bus
To DDR
Reg.
DQS
DQS
PIO
DQS
Strobe
PAD
sysIO
Buffer
Polarity Control
Logic
DI
DQS
DQSDEL
Calibration Bus
from DLL
Figure 2-33. DLL Calibration Bus and DQS/DQS Transition Distribution
Delay Control Bus
Polarity Control Bus
DQS Bus
DLL
DLL
2-27