欢迎访问ic37.com |
会员登录 免费注册
发布采购

LFEC33E-3FN672C 参数 Datasheet PDF下载

LFEC33E-3FN672C图片预览
型号: LFEC33E-3FN672C
PDF下载: 下载PDF文件 查看货源
内容描述: 的LatticeECP / EC系列数据手册 [LatticeECP/EC Family Data Sheet]
分类和应用:
文件页数/大小: 163 页 / 1036 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
 浏览型号LFEC33E-3FN672C的Datasheet PDF文件第6页浏览型号LFEC33E-3FN672C的Datasheet PDF文件第7页浏览型号LFEC33E-3FN672C的Datasheet PDF文件第8页浏览型号LFEC33E-3FN672C的Datasheet PDF文件第9页浏览型号LFEC33E-3FN672C的Datasheet PDF文件第11页浏览型号LFEC33E-3FN672C的Datasheet PDF文件第12页浏览型号LFEC33E-3FN672C的Datasheet PDF文件第13页浏览型号LFEC33E-3FN672C的Datasheet PDF文件第14页  
Architecture  
LatticeECP/EC Family Data Sheet  
Lattice Semiconductor  
Routing  
There are many resources provided in the LatticeECP/EC devices to route signals individually or as busses with  
related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing)  
segments.  
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).  
The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions. The x2 and  
x6 resources are buffered, the routing of both short and long connections between PFUs.  
The ispLEVER design tool suite takes the output of the synthesis tool and places and routes the design. Generally,  
the place and route tool is completely automatic, although an interactive routing editor is available to optimize the  
design.  
Clock Distribution Network  
The clock inputs are selected from external I/O, the sysCLOCK™ PLLs or routing. These clock inputs are fed  
through the chip via a clock distribution system.  
Primary Clock Sources  
LatticeECP/EC devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing.  
LatticeECP/EC devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There  
are four dedicated clock inputs, one on each side of the device. Figure 2-6 shows the 20 primary clock sources.  
Figure 2-6. Primary Clock Sources  
From Routing  
Clock Input  
From Routing  
PLL Input  
PLL Input  
PLL  
PLL  
20 Primary Clock Sources  
To Quadrant Clock Selection  
Clock Input  
Clock Input  
PLL  
PLL  
PLL Input  
PLL Input  
From Routing  
Clock Input  
From Routing  
Note: Smaller devices have two PLLs.  
2-7