Architecture
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Figure 2-4. Slice Diagram
To / From
Different slice / PFU
Slice
OFX1
F1
A1
CO
F
B1
C1
D1
Q1
LUT4 &
D
SUM
FF/
Latch
CARRY
CI
To
Routing
From
Routing
M1
M0
OFX0
LUT
Expansion
Mux
CO
A0
B0
F0
C0
LUT4 &
CARRY
F
D0
OFX0
Q0
SUM
D
FF/
CI
Latch
Control Signals
selected and
inverted per
CE
CLK
LSR
slice in routing
Interslice signals
are not shown
To / From
Different slice / PFU
Table 2-1. Slice Signal Descriptions
Function
Input
Type
Signal Names
Description
Data signal
A0, B0, C0, D0 Inputs to LUT4
A1, B1, C1, D1 Inputs to LUT4
Input
Data signal
Input
Multi-purpose
Multi-purpose
Control signal
Control signal
Control signal
Inter-PFU signal
Data signals
Data signals
Data signals
Data signals
Inter-PFU signal
M0
M1
Multipurpose Input
Input
Multipurpose Input
Clock Enable
Input
CE
Input
LSR
Local Set/Reset
System Clock
Fast Carry In1
Input
CLK
Input
FCIN
F0, F1
Q0, Q1
OFX0
OFX1
FCO
Output
Output
Output
Output
Output
LUT4 output register bypass signals
Register Outputs
Output of a LUT5 MUX
Output of a LUT6, LUT7, LUT82 MUX depending on the slice
For the right most PFU the fast carry chain output1
1. See Figure 2-3 for connection details.
2. Requires two PFUs.
2-4
LATTICE [ LATTICE SEMICONDUCTOR ]
