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LFEC33E-3FN672C 参数 Datasheet PDF下载

LFEC33E-3FN672C图片预览
型号: LFEC33E-3FN672C
PDF下载: 下载PDF文件 查看货源
内容描述: 的LatticeECP / EC系列数据手册 [LatticeECP/EC Family Data Sheet]
分类和应用:
文件页数/大小: 163 页 / 1036 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Architecture  
LatticeECP/EC Family Data Sheet  
Lattice Semiconductor  
Modes of Operation  
Each Slice is capable of four modes of operation: Logic, Ripple, RAM and ROM. The Slice in the PFF is capable of  
all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks.  
Table 2-2. Slice Modes  
Logic  
Ripple  
RAM  
SPR16x2  
N/A  
ROM  
PFU Slice  
PFF Slice  
LUT 4x2 or LUT 5x1  
LUT 4x2 or LUT 5x1  
2-bit Arithmetic Unit  
2-bit Arithmetic Unit  
ROM16x1 x 2  
ROM16x1 x 2  
Logic Mode: In this mode, the LUTs in each Slice are configured as 4-input combinatorial lookup tables. A LUT4  
can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this  
lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup  
tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other Slices.  
Ripple Mode: Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the fol-  
lowing functions can be implemented by each Slice:  
• Addition 2-bit  
• Subtraction 2-bit  
• Add/Subtract 2-bit using dynamic control  
• Up counter 2-bit  
• Down counter 2-bit  
• Ripple mode multiplier building block  
• Comparator functions of A and B inputs  
- A greater-than-or-equal-to B  
- A not-equal-to B  
- A less-than-or-equal-to B  
Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this  
configuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are  
generated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices.  
RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x1-bit memory.  
Through the combination of LUTs and Slices, a variety of different memories can be constructed.  
The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-  
ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3  
shows the number of Slices required to implement different distributed RAM primitives. Figure 2-5 shows the dis-  
tributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices, one Slice functions  
as the read-write port. The other companion Slice supports the read-only port. For more information about using  
RAM in LatticeECP/EC devices, please see the list of technical documentation at the end of this data sheet.  
Table 2-3. Number of Slices Required For Implementing Distributed RAM  
SPR16x2  
DPR16x2  
Number of slices  
1
2
Note: SPR = Single Port RAM, DPR = Dual Port RAM  
2-5