Architecture
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
grammed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after
adjustment and not relock until the t parameter has been satisfied. Additionally, the phase and duty cycle block
LOCK
allows the user to adjust the phase and duty cycle of the CLKOS output.
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated
with it: input clock divider, feedback divider, post scalar divider and secondary clock divider. The input clock divider
is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal.The post
scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the fre-
quency range. The secondary divider is used to derive lower frequency outputs.
Figure 2-11. PLL Diagram
Dynamic Delay Adjustment
LOCK
Input Clock
Divider
(CLKI)
Post Scalar
Divider
(CLKOP)
Phase/Duty
Select
CLKI
(from routing or
external pin)
Voltage
ConVtCroOlled
Oscillator
CLKOS
Delay
Adjust
CLKOP
CLKOK
RST
Secondary
Clock
Divider
Feedback
Divider
(CLKFB)
CLKFB
from CLKOP
(PLL internal),
from clock net
(CLKOP) or
(CLKOK)
from a user
clock (PIN or logic)
Figure 2-12 shows the available macros for the PLL. Table 2-5 provides signal description of the PLL Block.
Figure 2-12. PLL Primitive
CLKOP
RST
CLKI
CLKI
CLKOP
LOCK
CLKOS
CLKOK
LOCK
EPLLB
CLKFB
CLKFB
DDA MODE
DDAIZR
EHXPLLB
DDAOZR
DDAILAG
DDAOLAG
DDAODEL[2:0]
DDAIDEL[2:0]
2-10
LATTICE [ LATTICE SEMICONDUCTOR ]
