Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4000V/B/C Internal Timing Parameters
Over Recommended Operating Conditions
-5
-75
-10
Parameter
Description
Min. Max. Min. Max. Min. Max. Units
In/Out Delays
t
t
t
t
t
t
Input Buffer Delay
—
—
—
—
—
—
0.95
4.04
1.83
1.00
0.96
0.96
—
—
—
—
—
—
1.50
6.04
2.28
1.50
0.96
0.96
—
—
—
—
—
—
2.00
7.04
3.28
1.50
0.96
0.96
ns
ns
ns
ns
ns
ns
IN
Global OE Pin Delay
GOE
GCLK_IN
BUF
EN
Global Clock Input Buffer Delay
Delay through Output Buffer
Output Enable Time
Output Disable Time
DIS
Routing/GLB Delays
t
t
t
t
t
t
Delay through GRP
—
—
—
—
—
—
1.51
1.05
0.56
0.00
1.54
0.94
—
—
—
—
—
—
2.26
1.45
0.96
0.00
2.24
1.24
—
—
—
—
—
—
3.26
1.95
1.46
0.00
3.24
1.74
ns
ns
ns
ns
ns
ns
ROUTE
MCELL
INREG
FBK
Macrocell Delay
Input Buffer to Macrocell Register Delay
Internal Feedback Delay
5-PT Bypass Propagation Delay
Macrocell Propagation Delay
PDb
PDi
Register/Latch Delays
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
D-Register Setup Time (Global Clock)
D-Register Setup Time (Product Term Clock)
T-Register Setup Time (Global Clock)
T-Register Setup Time (Product Term Clock)
D-Register Hold Time
1.32
1.32
1.52
1.32
1.68
1.68
1.52
1.45
0.68
0.68
—
—
—
1.57
1.32
1.77
1.32
2.93
2.93
1.57
1.45
1.18
1.18
—
—
—
1.57
1.32
1.77
1.32
3.93
3.93
1.57
1.45
1.18
1.18
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
S
S_PT
ST
—
—
—
—
—
—
ST_PT
H
—
—
—
T-Register Hold Time
—
—
—
HT
D-Input Register Setup Time (Global Clock)
D-Input Register Setup Time (Product Term Clock)
D-Input Register Hold Time (Global Clock)
D-Input Register Hold Time (Product Term Clock)
Register Clock to Output/Feedback MUX Time
Clock Enable Setup Time
—
—
—
SIR
—
—
—
SIR_PT
HIR
—
—
—
—
—
—
HIR_PT
COi
0.52
—
0.67
—
1.17
—
2.25
1.88
1.32
1.32
1.17
—
2.25
1.88
1.57
1.32
1.17
—
2.25
1.88
1.57
1.32
1.17
—
CES
CEH
SL
Clock Enable Hold Time
—
—
—
Latch Setup Time (Global Clock)
—
—
—
Latch Setup Time (Product Term Clock)
Latch Hold Time
—
—
—
SL_PT
HL
—
—
—
Latch Gate to Output/Feedback MUX Time
0.33
0.25
0.33
0.25
0.33
0.25
GOi
Propagation Delay through Transparent Latch to Output/
Feedback MUX
—
—
—
PDLi
t
Asynchronous Reset or Set to Output/Feedback MUX
Delay
0.28
1.67
—
—
0.28
1.67
—
—
0.28
1.67
—
—
ns
ns
SRi
t
Asynchronous Reset or Set Recovery Time
SRR
Control Delays
t
t
t
t
GLB PT Clock Delay
—
—
—
—
1.12
0.87
1.83
2.51
—
—
—
—
1.12
0.87
1.83
3.41
—
—
—
—
0.62
0.87
1.83
3.41
ns
ns
ns
ns
BCLK
PTCLK
BSR
Macrocell PT Clock Delay
GLB PT Set/Reset Delay
Macrocell PT Set/Reset Delay
PTSR
29