Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4000V/B/C Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
Parameter
Description
-2.5
-2.7
-3
-3.5
Units
Propagation Delay through
Transparent Latch to Output/
Feedback MUX
t
—
0.25
—
0.25
—
0.25
—
0.25
ns
PDLi
Asynchronous Reset or Set to
Output/Feedback MUX Delay
t
t
0.28
1.67
—
—
0.28
1.67
—
—
0.28
1.67
—
—
0.28
1.67
—
—
ns
ns
SRi
Asynchronous Reset or Set
Recovery Time
SRR
Control Delays
t
t
t
t
t
t
GLB PT Clock Delay
—
—
—
—
—
—
1.12
0.87
1.83
1.11
2.83
1.83
—
—
—
—
—
—
1.12
0.87
1.83
1.41
4.13
2.13
—
—
—
—
—
—
1.12
0.87
1.83
1.51
5.33
2.33
—
—
—
—
—
—
1.12
0.87
1.83
1.61
5.33
2.83
ns
ns
BCLK
PTCLK
BSR
Macrocell PT Clock Delay
Block PT Set/Reset Delay
Macrocell PT Set/Reset Delay
Global PT OE Delay
ns
ns
PTSR
GPTOE
PTOE
ns
Macrocell PT OE Delay
ns
Timing v.3.2
Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.
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LATTICE [ LATTICE SEMICONDUCTOR ]
