Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4000Z External Switching Characteristics
Over Recommended Operating Conditions
-35
-37
-42
Parameter
Description1, 2, 3
Min.
Max.
Min.
Max.
Min.
Max.
Units
t
t
t
t
5-PT bypass combinatorial propagation delay
—
3.5
—
3.7
—
4.2
ns
PD
20-PT combinatorial propagation delay
through macrocell
—
4.4
—
—
4.7
—
—
5.7
—
ns
ns
ns
PD_MC
GLB register setup time before clock
2.2
2.4
2.5
2.7
2.7
2.9
S
GLB register setup time before clock with
T-type register
—
—
—
ST
GLB register setup time before clock, input
register path
t
1.0
—
1.1
—
1.3
—
ns
SIR
GLB register setup time before clock with zero
hold
t
t
t
2.0
0.0
0.0
—
—
—
2.1
0.0
0.0
—
—
—
2.6
0.0
0.0
—
—
—
ns
ns
ns
SIRZ
GLB register hold time after clock
H
GLB register hold time after clock with T-type
register
HT
GLB register hold time after clock, input
register path
t
t
1.0
0.0
—
—
1.0
0.0
—
—
1.3
0.0
—
—
ns
ns
HIR
GLB register hold time after clock, input
register path with zero hold
HIRZ
t
t
t
GLB register clock-to-output delay
External reset pin to output delay
External reset pulse duration
—
—
3.0
5.0
—
—
—
3.2
6.0
—
—
—
3.5
7.3
—
ns
ns
ns
CO
R
1.5
1.7
2.0
RW
Input to output local product term output
enable/disable
t
t
—
—
7.0
6.5
—
—
8.0
7.0
—
—
8.0
8.0
ns
ns
PTOE/DIS
Input to output global product term output
enable/disable
GPTOE/DIS
t
t
Global OE input to output enable/disable
Global clock width, high or low
—
4.5
—
—
4.5
—
—
4.8
—
ns
ns
GOE/DIS
1.0
1.5
1.8
CW
Global gate width low (for low transparent) or
high (for high transparent)
t
1.0
—
1.5
—
1.8
—
ns
GW
t
f
Input register clock width, high or low
Clock frequency with internal feedback
clock frequency with external feedback,
1.0
—
—
1.5
—
—
1.8
—
—
ns
WIR
4
267
250
220
MHz
MAX
t
(Ext.)
192
—
175
—
161
—
MHz
MAX
[1 / (t + t )]
S
CO
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
2. Measured using standard switching GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
Timing v.2.2
24
LATTICE [ LATTICE SEMICONDUCTOR ]
