Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4000V/B/C External Switching Characteristics (Cont.)
Over Recommended Operating Conditions
-5
-75
-10
Parameter
Description1, 2, 3
Min. Max. Min. Max. Min. Max. Units
t
5-PT bypass combinatorial propagation delay
20-PT combinatorial propagation delay through macrocell
GLB register setup time before clock
—
5.0
5.5
—
—
—
—
—
—
—
—
7.5
8.0
—
—
—
—
—
—
—
—
10.0
10.5
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
PD
t
t
t
t
t
t
t
t
—
—
—
PD_MC
S
3.0
3.2
1.2
2.2
0.0
0.0
1.0
4.5
4.7
1.7
2.7
0.0
0.0
1.0
5.5
5.5
1.7
2.7
0.0
0.0
1.0
GLB register setup time before clock with T-type register
GLB register setup time before clock, input register path
GLB register setup time before clock with zero hold
GLB register hold time after clock
—
ST
—
SIR
SIRZ
H
—
—
GLB register hold time after clock with T-type register
GLB register hold time after clock, input register path
—
HT
—
HIR
GLB register hold time after clock, input register path with
zero hold
t
0.0
—
0.0
—
0.0
—
ns
HIRZ
t
t
t
t
t
t
t
GLB register clock-to-output delay
—
—
3.4
6.3
—
—
—
4.5
9.0
—
—
—
6.0
10.5
—
ns
ns
ns
ns
ns
ns
ns
CO
External reset pin to output delay
R
External reset pulse duration
2.0
—
4.0
—
4.0
—
RW
Input to output local product term output enable/disable
Input to output global product term output enable/disable
Global OE input to output enable/disable
Global clock width, high or low
7.0
9.0
5.0
—
9.0
10.3
7.0
—
10.5
12.0
8.0
PTOE/DIS
GPTOE/DIS
GOE/DIS
CW
—
—
—
—
—
—
2.2
3.3
4.0
—
Global gate width low (for low transparent) or high (for
high transparent)
t
2.2
—
3.3
—
4.0
—
ns
GW
t
f
f
Input register clock width, high or low
Clock frequency with internal feedback
2.2
227
156
—
—
—
3.3
168
111
—
—
—
4.0
125
86
—
—
—
ns
MHz
WIR
4
MAX
(Ext.) Clock frequency with external feedback, [1/ (t + t )]
MHz
MAX
S
CO
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
Timing v.3.2
23
LATTICE [ LATTICE SEMICONDUCTOR ]
