Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4000V/B/C External Switching Characteristics
Over Recommended Operating Conditions
-25
-27
-3
-35
Parameter
Description1, 2, 3
Min. Max. Min. Max. Min. Max. Min. Max. Units
5-PT bypass combinatorial propagation
delay
t
—
2.5
—
2.7
—
3.0
—
3.5
ns
PD
20-PT combinatorial propagation delay
through macrocell
t
t
t
—
3.2
—
—
3.5
—
—
3.8
—
—
4.2
—
ns
ns
ns
PD_MC
GLB register setup time before clock
1.8
2.0
1.8
2.0
2.0
2.2
2.0
2.2
S
GLB register setup time before clock
with T-type register
—
—
—
—
ST
GLB register setup time before clock,
input register path
t
0.7
—
1.0
—
1.0
—
1.0
—
ns
SIR
GLB register setup time before clock
with zero hold
t
t
t
1.7
0.0
0.0
—
—
—
2.0
0.0
0.0
—
—
—
2.0
0.0
0.0
—
—
—
2.0
0.0
0.0
—
—
—
ns
ns
ns
SIRZ
GLB register hold time after clock
H
GLB register hold time after clock with
T-type register
HT
GLB register hold time after clock, input
register path
t
t
0.9
0.0
—
—
1.0
0.0
—
—
1.0
0.0
—
—
1.0
0.0
—
—
ns
ns
HIR
GLB register hold time after clock, input
register path with zero hold
HIRZ
t
t
t
GLB register clock-to-output delay
External reset pin to output delay
External reset pulse duration
—
—
2.2
3.5
—
—
—
2.7
4.0
—
—
—
2.7
4.4
—
—
—
2.7
4.5
-
ns
ns
ns
CO
R
1.5
1.5
1.5
1.5
RW
Input to output local product term output
enable/disable
t
t
—
—
4.0
5.0
—
—
4.5
6.5
—
—
5.0
8.0
—
—
5.5
8.0
ns
ns
PTOE/DIS
Input to output global product term
output enable/disable
GPTOE/DIS
t
t
Global OE input to output enable/disable
Global clock width, high or low
—
3.0
—
—
3.5
—
—
4.0
—
—
4.5
—
ns
ns
GOE/DIS
1.1
1.3
1.3
1.3
CW
Global gate width low (for low
transparent) or high (for high transparent)
t
1.1
—
1.3
—
1.3
—
1.3
—
ns
GW
t
f
Input register clock width, high or low
Clock frequency with internal feedback
Clock frequency with external feedback,
1.1
—
—
1.3
—
—
1.3
—
—
1.3
—
—
ns
WIR
4
400
333
322
322
MHz
MAX
f
(Ext.)
250
—
222
—
212
—
212
—
MHz
MAX
[1/ (t + t )]
S
CO
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
Timing v.3.2
22
LATTICE [ LATTICE SEMICONDUCTOR ]
