Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
I/O DC Electrical Characteristics
Over Recommended Operating Conditions
V
V
IH
1
1
IL
V
V
I
I
OH
OL
OH
OL
Standard
LVTTL
Min (V)
Max (V)
Min (V)
Max (V) Max (V)
Min (V)
(mA) (mA)
0.40
V
V
V
V
V
V
V
V
V
V
- 0.40
8.0
0.1
8.0
0.1
8.0
0.1
2.0
0.1
2.0
0.1
1.5
1.5
-4.0
-0.1
-4.0
-0.1
-4.0
-0.1
-2.0
-0.1
-2.0
-0.1
-0.5
-0.5
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
-0.3
0.80
0.80
0.70
0.63
2.0
2.0
5.5
0.20
- 0.20
- 0.40
- 0.20
- 0.40
- 0.20
- 0.45
- 0.20
- 0.45
- 0.20
0.40
LVCMOS 3.3
LVCMOS 2.5
-0.3
-0.3
-0.3
-0.3
5.5
0.20
0.40
1.70
1.17
3.6
0.20
0.40
LVCMOS 1.8
(4000V/B)
3.6
0.20
0.40
LVCMOS 1.8
(4000C/Z)
0.35 * V
1.08
0.65 * V
1.5
3.6
CC
CC
0.20
PCI 3.3 (4000V/B)
PCI 3.3 (4000C/Z)
-0.3
-0.3
5.5
5.5
0.1 V
0.1 V
0.9 V
0.9 V
CCO
CCO
0.3 * 3.3 * (V / 1.8) 0.5 * 3.3 * (V / 1.8)
CC
CC
CCO
CCO
1. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of
the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND
connections or between the last GND in a bank and the end of a bank.
20
LATTICE [ LATTICE SEMICONDUCTOR ]
