Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
I/O Recommended Operating Conditions
V
(V)1
CCO
Standard
Min.
3.0
Max.
LVTTL
3.6
3.6
3.6
2.7
1.95
3.6
LVCMOS 3.3
Extended LVCMOS 3.32
LVCMOS 2.5
LVCMOS 1.8
PCI 3.3
3.0
2.7
2.3
1.65
3.0
1. Typical values for V
are the average of the min. and max. values.
CCO
2. ispMACH 4000Z only.
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
Input Leakage Current (ispMACH
4000Z)
1, 4
I , I
0 ≤ V < V
—
—
0.5
1
µA
IL IH
IN
CCO
Input High Leakage Current
(ispMACH 4000Z)
1
I
V
< V ≤ 5.5V
—
10
µA
IH
CCO
IN
0 ≤ V ≤ 3.6V, T = 105°C
—
—
—
—
10
15
µA
µA
Input Leakage Current (ispMACH
4000V/B/C)
IN
j
1
I , I
IL IH
0 ≤ V ≤ 3.6V, T = 130°C
IN
j
3.6V < V ≤ 5.5V, T = 105°C
IN
j
—
—
—
—
—
—
20
50
µA
µA
µA
µA
3.0V ≤ V
≤ 3.6V
Input High Leakage Current
(ispMACH 4000V/B/C)
CCO
1,2
I
IH
3.6V < V ≤ 5.5V, T = 130°C
IN
CCO
j
3.0V ≤ V
≤ 3.6V
I/O Weak Pull-up Resistor Current
(ispMACH 4000Z)
0 ≤ V ≤ 0.7V
-30
-30
-150
-200
IN
CCO
I
PU
I/O Weak Pull-up Resistor Current
(ispMACH 4000V/B/C)
0 ≤ V ≤ 0.7V
IN
CCO
I
I
I
I
I
I/O Weak Pull-down Resistor Current V (MAX) ≤ V ≤ V (MIN)
30
30
-30
—
—
—
—
—
—
—
150
—
µA
µA
µA
µA
µA
V
PD
IL
IN
IH
Bus Hold Low Sustaining Current
Bus Hold High Sustaining Current
Bus Hold Low Overdrive Current
Bus Hold High Overdrive Current
Bus Hold Trip Points
V
V
= V (MAX)
IL
BHLS
BHHS
BHLO
BHHO
IN
IN
= 0.7 V
—
CCO
0V ≤ V ≤ V
150
-150
IN
BHT
V
≤ V ≤ V
CCO
—
BHT
IN
V
—
V
* 0.35
V
* 0.65
CCO
BHT
CCO
V
V
V
V
V
V
= 3.3V, 2.5V, 1.8V
—
—
—
—
—
—
—
—
—
—
—
—
CCO
C
C
C
I/O Capacitance3
8
6
6
pf
pf
pf
1
2
3
= 1.8V, V = 0 to V (MAX)
CC
IO
IH
= 3.3V, 2.5V, 1.8V
CCO
Clock Capacitance3
Global Input Capacitance3
= 1.8V, V = 0 to V (MAX)
CC
IO
IH
= 3.3V, 2.5V, 1.8V
CCO
= 1.8V, V = 0 to V (MAX)
CC
IO
IH
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not
measured with the output driver active. Bus maintenance circuits are disabled.
2. 5V tolerant inputs and I/O should only be placed in banks where 3.0V ≤ V
≤ 3.6V.
CCO
3. T = 25°C, f = 1.0MHz
A
4. I excursions of up to 1.5µA maximum per pin above the spec limit may be observed for certain voltage conditions on no more than 10% of
IH
the device’s I/O pins.
16
LATTICE [ LATTICE SEMICONDUCTOR ]
