欢迎访问ic37.com |
会员登录 免费注册
发布采购

ISPLSI2032A-80LT44 参数 Datasheet PDF下载

ISPLSI2032A-80LT44图片预览
型号: ISPLSI2032A-80LT44
PDF下载: 下载PDF文件 查看货源
内容描述: 在系统可编程高密度PLD [In-System Programmable High Density PLD]
分类和应用: 可编程逻辑器件输入元件时钟
文件页数/大小: 15 页 / 145 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
 浏览型号ISPLSI2032A-80LT44的Datasheet PDF文件第7页浏览型号ISPLSI2032A-80LT44的Datasheet PDF文件第8页浏览型号ISPLSI2032A-80LT44的Datasheet PDF文件第9页浏览型号ISPLSI2032A-80LT44的Datasheet PDF文件第10页浏览型号ISPLSI2032A-80LT44的Datasheet PDF文件第12页浏览型号ISPLSI2032A-80LT44的Datasheet PDF文件第13页浏览型号ISPLSI2032A-80LT44的Datasheet PDF文件第14页浏览型号ISPLSI2032A-80LT44的Datasheet PDF文件第15页  
Specifications ispLSI 2032/A  
Pin Description  
48-PIN TQFP  
44-PIN PLCC  
44-PIN TQFP  
PIN NUMBERS  
PIN NUMBERS  
PIN NUMBERS  
NAME  
DESCRIPTION  
9, 10, 11, 13,  
14, 15, 16, 17,  
20, 21, 22, 23,  
25, 26, 27, 28,  
33, 34, 35, 37,  
38, 39, 40, 41,  
44, 45, 46, 47,  
I/O 0 - I/O 3  
I/O 4 - I/O 7  
15, 16, 17, 18,  
19, 20, 21, 22,  
25, 26, 27, 28,  
29, 30, 31, 32,  
37, 38, 39, 40,  
41, 42, 43, 44,  
3, 4, 5, 6,  
7, 8, 9, 10  
9, 10, 11, 12,  
13, 14, 15, 16,  
19, 20, 21, 22,  
23, 24, 25, 26,  
31 32, 33, 34,  
35, 36, 37, 38,  
41, 42, 43, 44,  
Input/Output Pins — These are the general purpose  
I/O pins used by the logic array.  
I/O 8 - I/O 11  
I/O 12 - I/O 15  
I/O 16 - I/O 19  
I/O 20 - I/O 23  
I/O 24 - I/O 27  
I/O 28 - I/O 31  
1, 2, 3,  
4
1, 2, 3,  
4
40  
5
GOE 0  
Y0  
2
Global Output Enable input pin.  
43  
5
11  
Dedicated Clock input. This clock input is connected to  
one of the clock inputs of all the GLBs on the device.  
RESET/Y1  
35  
This pin performs two functions:  
29  
31  
- Dedicated clock input. This clock input is brought  
into the Clock Distribution Network, and can optionally  
be routed to any GLB and/or I/O cell on the device.  
- Active Low (0) Reset pin which resets all of the GLB  
and I/O registers in the device.  
7
8
ispEN  
13  
14  
7
8
Input — Dedicated in-system programming enable  
input pin. This pin is brought low to enable the  
programming mode. The MODE, SDI, SDO and SCLK  
controls become active.  
2
SDI/IN 0  
Input — This pin performs two functions. When ispEN  
is logic low, it functions as an input pin to load  
programming data into the device. SDI/IN0 also is used  
as one of the two control pins for the isp state machine.  
When ispEN is high, it functions as a dedicated input  
pin.  
32  
19  
MODE  
36  
24  
30  
18  
Input — When in ISP Mode, controls operation of ISP  
state machine.  
2
SDO/IN 1  
Output/Input — This pin performs two functions. When  
ispEN is logic low, it functions as an output pin to read  
serial shift register data. When ispEN is high, it  
functions as a dedicated input pin.  
2
SCLK/Y2  
33  
27  
29  
Input — This pin performs two functions. When  
ispEN is logic low, it functions as a clock pin for the  
Serial Shift Register. When ispEN is high, it  
functions as a dedicated clock input. This clock input  
is brought into the Clock Distribution Network and  
can be routed to any GLB and/or I/O cell on the  
device.  
GND  
VCC  
1, 23  
12, 34  
17, 39  
6, 28  
18, 42  
6, 30  
Ground (GND)  
V
CC  
1
NC  
No Connect.  
12, 24, 36, 48  
Table 2-0002A-08isp/2032  
1. NC pins are not to be connected to any active signals, VCC or GND.  
2. Pins have dual function capability.  
11