DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2/M Internal Switching Characteristics1
Over Recommended Operating Conditions
-7
-6
-5
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
PFU/PFF Logic Mode Timing
t
t
LUT4 delay (A to D inputs to F output)
LUT6 delay (A to D inputs to OFX output)
—
—
0.180
0.304
—
—
0.198
0.331
—
—
0.216
0.358
ns
ns
LUT4_PFU
LUT6_PFU
Set/Reset to output of PFU (Asynchro-
nous)
t
—
0.600
—
0.655
—
0.711
ns
LSR_PFU
t
t
t
t
Clock to Mux (M0,M1) Input Setup Time
Clock to Mux (M0,M1) Input Hold Time
Clock to D input setup time
0.128
-0.051
0.061
0.002
—
—
—
—
0.129
-0.049
0.071
0.003
—
—
—
—
0.129
-0.046
0.081
0.003
—
—
—
—
ns
ns
ns
ns
SUM_PFU
HM_PFU
SUD_PFU
HD_PFU
Clock to D input hold time
Clock to Q delay, (D-type Register Configu-
ration)
t
—
0.285
—
0.309
—
0.333
ns
CK2Q_PFU
PFU Dual Port Memory Mode Timing
t
t
t
t
t
t
t
Clock to Output (F Port)
Data Setup Time
—
0.902
—
—
1.083
—
—
1.263
—
ns
ns
ns
ns
ns
ns
ns
CORAM_PFU
SUDATA_PFU
HDATA_PFU
-0.172
0.199
-0.245
0.246
-0.122
0.132
-0.205
0.235
-0.284
0.285
-0.145
0.156
-0.238
0.271
-0.323
0.324
-0.168
0.180
Data Hold Time
—
—
—
Address Setup Time
Address Hold Time
—
—
—
SUADDR_PFU
HADDR_PFU
SUWREN_PFU
HWREN_PFU
—
—
—
Write/Read Enable Setup Time
Write/Read Enable Hold Time
—
—
—
—
—
—
PIC Timing
PIO Input/Output Buffer Timing
t
t
Input Buffer Delay (LVCMOS25)
Output Buffer Delay (LVCMOS25)
—
—
0.613
1.115
—
—
0.681
1.115
—
—
0.749
1.343
ns
ns
IN_PIO
OUT_PIO
IOLOGIC Input/Output Timing
Input Register Setup Time (Data Before
Clock)
t
t
0.596
—
—
0.645
—
—
0.694
—
—
ns
ns
SUI_PIO
Input Register Hold Time (Data after
Clock)
-0.570
-0.614
-0.658
HI_PIO
t
t
t
t
t
Output Register Clock to Output Delay
Input Register Clock Enable Setup Time
Input Register Clock Enable Hold Time
Set/Reset Setup Time
—
0.61
—
—
0.66
—
—
0.72
—
ns
ns
ns
ns
ns
COO_PIO
SUCE_PIO
HCE_PIO
0.032
-0.022
0.184
-0.080
0.037
-0.025
0.201
-0.086
0.041
-0.028
0.217
-0.093
—
—
—
—
—
—
SULSR_PIO
HLSR_PIO
Set/Reset Hold Time
—
—
—
EBR Timing
Clock (Read) to output from Address or
Data
t
t
—
—
2.51
0.33
—
—
2.75
0.36
—
—
2.99
0.39
ns
ns
CO_EBR
Clock (Write) to output from EBR output
Register
COO_EBR
t
t
t
t
t
Setup Data to EBR Memory
Hold Data to EBR Memory
Setup Address to EBR Memory
Hold Address to EBR Memory
-0.157
0.173
-0.115
0.138
—
—
—
—
—
-0.181
0.195
-0.130
0.155
-0.149
—
—
—
—
—
-0.205
0.217
-0.145
0.172
-0.170
—
—
—
—
—
ns
ns
ns
ns
ns
SUDATA_EBR
HDATA_EBR
SUADDR_EBR
HADDR_EBR
SUWREN_EBR
Setup Write/Read Enable to PFU Memory -0.128
3-28
LATTICE [ LATTICE SEMICONDUCTOR ]
