DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2/M Internal Switching Characteristics1 (Continued)
Over Recommended Operating Conditions
-7
-6
-5
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
t
t
Hold Write/Read Enable to PFU Memory
0.139
—
0.156
—
0.173
—
ns
HWREN_EBR
Clock Enable Setup Time to EBR Output
Register
0.123
-0.081
—
—
—
0.134
-0.090
—
—
—
0.145
-0.100
—
—
—
ns
ns
ns
ns
ns
SUCE_EBR
HCE_EBR
RSTO_EBR
SUBE_EBR
HBE_EBR
Clock Enable Hold Time to EBR Output
Register
t
t
t
t
Reset To Output Delay Time from EBR
Output Register
1.03
—
1.15
—
1.26
—
Byte Enable Set-Up Time to EBR Output
Register
-0.115
0.138
-0.130
0.155
-0.145
0.172
Byte Enable Hold Time to EBR Output
Register
—
—
—
GPLL Parameters
t
Reset Recovery to Rising Clock
Reset Recovery to Rising Clock
1.00
1.00
—
—
1.00
1.00
—
—
1.00
1.00
—
—
ns
ns
RSTREC_GPLL
SPLL Parameters
t
RSTREC_SPLL
DSP Block Timing2,3
t
t
t
t
t
t
t
t
t
t
t
Input Register Setup Time
0.12
0.02
2.18
-0.68
4.26
-1.25
—
—
—
0.13
-0.01
2.42
-0.77
4.71
-1.40
—
—
—
0.14
-0.03
2.66
-0.86
5.16
-1.54
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SUI_DSP
HI_DSP
Input Register Hold Time
Pipeline Register Setup Time
Pipeline Register Hold Time
—
—
—
SUP_DSP
tHP_DSP
SUO_DSP
HO_DSP
—
—
—
Output Register Setup Time
—
—
—
Output Register Hold Time
—
—
—
Input Register Clock to Output Time
Pipeline Register Clock to Output Time
Output Register Clock to Output Time
AddSub Input Register Setup Time
AddSub Input Register Hold Time
3.92
1.87
0.50
—
4.30
1.98
0.52
—
4.68
2.08
0.55
—
COI_DSP
COP_DSP
COO_DSP
SUADDSUB
HADDSUB
—
—
—
—
—
—
-0.24
0.27
-0.26
0.29
-0.28
0.32
—
—
—
1. Internal parameters are characterized but not tested on every device.
2. These parameters apply to LatticeECP devices only.
3. DSP Block is configured in Multiply Add/Sub 18x18 Mode.
Timing v.A 0.11
3-29
LATTICE [ LATTICE SEMICONDUCTOR ]
