DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2/M External Switching Characteristics9 (Continued)
Over Recommended Operating Conditions
-7
-6
-5
Parameter
Description
Device
ECP2-20
ECP2-35
ECP2-50
ECP2-70
Min.
—
—
—
—
—
—
—
—
—
Max.
280
280
280
280
230
230
230
230
230
Min.
—
Max.
280
280
280
280
230
230
230
230
230
Min.
—
—
—
—
—
—
—
—
—
Max.
280
280
280
280
230
230
230
230
230
Units
ps
—
ps
—
ps
—
ps
t
Data Invalid Before Clock (Transmit) ECP2M20
—
ps
DIBSPI
ECP2M35
ECP2M50
ECP2M70
ECP2M100
—
ps
—
ps
—
ps
—
ps
XGMII I/O Pin Parameters (312 Mbps)5
t
t
t
t
Data Setup Before Read Clock
Data Hold After Read Clock
Data Valid Before Clock
ECP2/M
ECP2/M
ECP2/M
ECP2/M
480
480
960
960
—
—
—
—
480
480
960
960
—
—
—
—
480
480
960
960
—
—
—
—
ps
ps
ps
ps
SUXGMII
HXGMII
DVBCKXGMII
DVACKXGMII
Data Valid After Clock
Primary
7
f
t
t
Frequency for Primary Clock Tree
ECP2/M
—
0.95
—
420
—
—
1.19
—
357
—
—
2.00
—
311
—
MHz
ns
MAX_PRI
Clock Pulse Width for Primary Clock ECP2/M
Primary Clock Skew Within a Bank ECP2/M
W_PRI
300
360
420
ps
SKEW_PRI
Edge Clock
7
f
t
Frequency for Edge Clock
ECP2/M
ECP2/M
—
420
—
—
357
—
—
311
—
MHz
ns
MAX_EDGE
Clock Pulse Width for Edge Clock
0.95
1.19
2.00
W_EDGE
Edge Clock Skew Within an Edge of
the Device
t
ECP2/M
—
300
—
360
—
420
ps
SKEW_EDGE
1. General timing numbers based on LVCMOS 2.5, 12mA, 0pf load.
2. DDR timing numbers based on SSTL25 for BGA packages only.
3. DDR2 timing numbers based on SSTL18 for BGA packages only.
4. SPI4.2 and SFI4 timing numbers based on LVDS25 for BGA packages only.
5. XGMII timing numbers based on HSTL class I. A corresponding left/right dedicated clock buffer is used when using the SPI4.2 interface to
the left or right edge of the device. For SPI4.2 mode, the software tool will help in selecting the appropriate clock buffer.
6. IP will be used to support DDR and DDR2 memory data rates down to 95MHz.This approach uses a free-running clock and PFU register to
sample the data instead of the hardwired DDR memory interface.
7. Using the LVDS I/O standard.
8. ECP2-6 and ECP2-12 do not support SPI4.2
9. The AC numbers do not apply to PCLK6 and PCLK7.
10. Applies to CLKOP only.
11. Please refer to technical note TN1159, LatticeECP2M Pin Assignment Recommendations for best performance.
Timing v.A 0.11
3-25
LATTICE [ LATTICE SEMICONDUCTOR ]
