DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Timing Diagrams
Figure 3-9. Read/Write Mode (Normal)
CLKA
CSA
WEA
ADA
DIA
A0
A1
D1
A0
A1
A0
tSU tH
D0
tCO_EBR
tCO_EBR
tCO_EBR
D0
D0
D1
DOA
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.
Figure 3-10. Read/Write Mode with Input and Output Registers
CLKA
CSA
WEA
ADA
A1
A0
A1
D1
A0
A0
t
t
H
SU
DIA
D0
t
t
COO_EBR
COO_EBR
DOA (Regs)
D1
D0
Mem(n) data from previous read
output is only updated during a read cycle
3-30
LATTICE [ LATTICE SEMICONDUCTOR ]
