DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2/M External Switching Characteristics9 (Continued)
Over Recommended Operating Conditions
-7
-6
-5
Parameter
Description
Device
LFE2-6
Min.
1.40
1.40
1.40
1.40
1.40
1.40
1.40
1.40
1.40
1.40
1.40
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
1.70
1.70
1.70
1.70
1.70
1.70
1.70
1.70
1.70
1.70
1.70
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
1.90
1.90
1.90
1.90
1.90
1.90
1.90
1.90
1.90
1.90
1.90
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LFE2-12
LFE2-20
LFE2-35
LFE2-50
LFE2-70
LFE2M20
LFE2M35
LFE2M50
LFE2M70
LFE2M100
LFE2-6
Clock to Data Setup - PIO Input
Register with Data Input Delay
t
SU_DEL
LFE2-12
LFE2-20
LFE2-35
LFE2-50
LFE2-70
LFE2M20
LFE2M35
LFE2M50
LFE2M70
LFE2M100
Clock to Data Hold - PIO Input Reg-
ister with Input Data Delay
t
f
H_DEL
Clock Frequency of I/O Register and
PFU Register
ECP2/M
—
420
—
357
—
311
MHz
MAX_IO
General I/O Pin Parameters (using Edge Clock without PLL)1
LFE2-6
—
—
—
—
—
—
—
—
—
—
—
2.60
2.60
2.60
2.60
2.60
2.60
2.60
2.60
3.10
3.10
3.10
—
—
—
—
—
—
—
—
—
—
—
2.90
2.90
2.90
2.90
2.90
2.90
2.90
2.90
3.40
3.40
3.40
—
—
—
—
—
—
—
—
—
—
—
3.20
3.20
3.20
3.20
3.20
3.20
3.20
3.20
3.70
3.70
3.70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LFE2-12
LFE2-20
LFE2-35
LFE2-50
Clock to Output - PIO Output
Register
t
LFE2-70
COE
LFE2M20
LFE2M35
LFE2M50
LFE2M70
LFE2M100
3-20
LATTICE [ LATTICE SEMICONDUCTOR ]
