DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Register-to-Register Performance (Continued)
Function
-7 Timing
Units
9x9 Multiplier (All Registers)
420
MHz
36x36 Multiplier
(All Registers)
372
295
420
MHz
MHz
MHz
18x18 Multiplier/Accumulate (Input and
Output Registers)
18x18 Multiplier-Add/Sub-Sum (All Reg-
isters)
DSP IP Functions
16-Tap Fully-Parallel FIR Filter
304
227
223
MHz
MHz
MHz
1024-pt, Radix 4, Decimation in
Frequency FFT
8x8 Matrix Multiplier
Timing v.A 0.11
Derating Timing Tables
Logic timing provided in the following sections of this data sheet and the ispLEVER design tools are worst case
numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be
much better than the values given in the tables. The ispLEVER design tool can provide logic timing numbers at a
particular temperature and voltage.
3-18
LATTICE [ LATTICE SEMICONDUCTOR ]
